EP20K400CB652C7 Altera, EP20K400CB652C7 Datasheet - Page 31

• Manufacturer Part Number: EP20K400CB652C7
• Description: APEX 20KC
• Manufacturer: Altera

utclock
utclken
ress[ ]
nclken
nclock
data[ ]
Altera Corporation
Figure 20. ESB in Read/Write Clock Mode
Note to
(1)
wren
Dedicated Clocks
All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset.
Figure
4
Dedicated Inputs &
Global Signals
20:
4
Read/Write Clock Mode
The read/write clock mode contains two clocks. One clock controls all
registers associated with writing: data input, WE, and write address. The
other clock controls all registers associated with reading: read enable
(RE), read address, and data output. The ESB also supports clock enable
and asynchronous clear signals; these signals also control the read and
write registers independently. Read/write clock mode is commonly used
for applications where reads and writes occur at different system
frequencies.
D
ENA
D
ENA
Q
Q
Figure 20
Note (1)
Generator
D
ENA
Pulse
Write
Q
shows the ESB in read/write clock mode.
APEX 20KC Programmable Logic Device Data Sheet
Data In
Address
Write Enable
RAM/ROM
1,024 × 2
2,048 × 1
Data Out
128 × 16
256 × 8
512 × 4
D
ENA
Q
To MegaLAB,
FastTrack &
Local
Interconnect
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