HUF76407D3ST Fairchild Semiconductor, HUF76407D3ST Datasheet

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HUF76407D3ST

Manufacturer Part Number
HUF76407D3ST
Description
MOSFET N-CH 60V 12A DPAK
Manufacturer
Fairchild Semiconductor
Series
UltraFET™r
Datasheet

Specifications of HUF76407D3ST

Fet Type
MOSFET N-Channel, Metal Oxide
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
92 mOhm @ 13A, 10V
Drain To Source Voltage (vdss)
60V
Current - Continuous Drain (id) @ 25° C
12A
Vgs(th) (max) @ Id
3V @ 250µA
Gate Charge (qg) @ Vgs
11.3nC @ 10V
Input Capacitance (ciss) @ Vds
350pF @ 25V
Power - Max
38W
Mounting Type
Surface Mount
Package / Case
DPak, TO-252 (2 leads+tab), SC-63
Configuration
Single
Transistor Polarity
N-Channel
Resistance Drain-source Rds (on)
0.077 Ohms
Drain-source Breakdown Voltage
60 V
Gate-source Breakdown Voltage
+/- 16 V
Continuous Drain Current
11 A
Power Dissipation
38 W
Maximum Operating Temperature
+ 175 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 55 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
©2001 Fairchild Semiconductor Corporation
11A, 60V, 0.107 Ohm, N-Channel, Logic
Level UltraFET® Power MOSFET
Packaging
Symbol
Absolute Maximum Ratings
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Drain to Gate Voltage (R
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Drain Current
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Maximum Temperature for Soldering
NOTE:
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1. T
Continuous (T
Continuous (T
Continuous (T
Continuous (T
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Derate Above 25
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
(FLANGE)
DRAIN
J
= 25
JEDEC TO-251AA
HUF76407D3
o
C to 150
C
C
C
C
= 25
= 25
= 135
= 135
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
o
C.
o
o
C, V
C, V
o
o
GS
G
C, V
C, V
SOURCE
DRAIN
= 20k Ω ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
GS
GATE
GS
GS
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
S
SOURCE
T
Data Sheet
GATE
For severe environments, see our Automotive HUFA series.
C
= 25
JEDEC TO-252AA
HUF76407D3S
o
C, Unless Otherwise Specified
(FLANGE)
DRAIN
Features
• Ultra Low On-Resistance
• Simulation Models
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Switching Time vs R
Ordering Information
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-252AA variant in tape and reel, e.g., HUF76407D3ST.
HUF76407D3
HUF76407D3S
- r
- r
- Temperature Compensated PSPICE® and SABER™
- Spice and SABER Thermal Impedance Models
- www.fairchildsemi.com
PART NUMBER
HUF76407D3, HUF76407D3S
Electrical Models
DS(ON)
DS(ON)
December 2001
J
, T
= 0.092 Ω,
= 0.107 Ω,
DGR
DSS
STG
pkg
DM
GS
D
D
D
D
D
L
TO-251AA
TO-252AA
GS
V
V
PACKAGE
GS
GS
Figures 6, 14, 15
Curves
HUF76407D3S
HUF76407D3,
= 10V
= 5V
-55 to 175
Figure 4
0.25
± 16
300
260
60
60
11
12
38
6
6
HUF76407D3, HUF76407D3S Rev. B
76407D
76407D
BRAND
UNITS
W/
o
o
o
W
V
V
V
A
A
A
A
C
C
C
o
C

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HUF76407D3ST Summary of contents

Page 1

... UIS Rating Curve • Switching Time vs R Ordering Information PART NUMBER HUF76407D3 HUF76407D3S NOTE: When ordering, use the entire part number. Add the suffi obtain the TO-252AA variant in tape and reel, e.g., HUF76407D3ST Unless Otherwise Specified = 0.092 Ω, = 10V 0.107 Ω ...

Page 2

... CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ©2001 Fairchild Semiconductor Corporation o C, Unless Otherwise Specified SYMBOL TEST CONDITIONS = 250 µ (Figure 12) ...

Page 3

... SINGLE PULSE 0. FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 200 100 V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION ©2001 Fairchild Semiconductor Corporation 150 175 125 o C) FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT RECTANGULAR PULSE DURATION ( PULSE WIDTH (s) FIGURE 4. PEAK CURRENT CAPABILITY 15 ...

Page 4

... DUTY CYCLE = 0.5% MAX 120 GATE TO SOURCE VOLTAGE (V) GS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT ©2001 Fairchild Semiconductor Corporation (Continued) 100 100µs 1ms 10ms 100 200 NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING ...

Page 5

... V , DRAIN TO SOURCE VOLTAGE (V) DS FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 150 V = 4.5V 30V 100 GATE TO SOURCE RESISTANCE (Ω) GS FIGURE 15. SWITCHING TIME vs GATE RESISTANCE ©2001 Fairchild Semiconductor Corporation (Continued 250µ 120 160 200 o C) FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN ISS RSS ...

Page 6

... Test Circuits and Waveforms VARY t TO OBTAIN P R REQUIRED PEAK FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT g(REF) FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 21. SWITCHING TIME TEST CIRCUIT ©2001 Fairchild Semiconductor Corporation DUT 0.01Ω DUT g(REF DUT DSS FIGURE 18. UNCLAMPED ENERGY WAVEFORMS ...

Page 7

... S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0 VOFF= -0.5) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ©2001 Fairchild Semiconductor Corporation DPLCAP 10 RSLC2 ...

Page 8

... Fairchild Semiconductor Corporation DPLCAP 10 RSLC2 - 6 ESG 8 EVTHRES + ...

Page 9

... Fairchild Semiconductor Corporation JUNCTION th RTHERM1 CTHERM1 6 RTHERM2 CTHERM2 5 RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 RTHERM5 ...

Page 10

... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ACEx™ FAST Bottomless™ FASTr™ FRFET™ CoolFET™ GlobalOptoisolator™ CROSSVOLT™ GTO™ DenseTrench™ ...

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