PIC16F1526T-I/PT Microchip Technology, PIC16F1526T-I/PT Datasheet
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... Microchip Technology Inc. PIC16(L)F1526/27 64-Pin Flash Microcontrollers with nanoWatt XLP Technology Preliminary Data Sheet DS41458B ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... In-Circuit Serial Programming™ (ICSP™) via two pins • In-Circuit Debug (ICD) via Two Pins • Enhanced Low-Voltage Programming (LVP) • Power-Saving Sleep mode 2011 Microchip Technology Inc. PIC16(L)F1526/27 Extreme Low-Power Management PIC16LF1526/27 with nanoWatt XLP: • Sleep mode 1.8V, typical • ...
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... Timers I/Os (bytes) (ch) 8/16-bit 768 54 30 6/3 1536 PIC16(L)F1526 PIC16(L)F1527 for list of pin peripheral Preliminary MSSP EUSART CCP 2 (I C™/SPI RB0 48 RB1 47 RB2 46 RB3 45 RB4 44 RB5 43 RB6 RA6 40 RA7 RB7 37 RC5 36 RC4 35 RC3 34 RC2 33 2011 Microchip Technology Inc. ...
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... RG3 7 V /MCLR/RG5 PP 8 RG4 RF7 12 RF6 RF5 13 RF4 14 RF3 15 RF2 See Note 1: TABLE 1-2: “PIC16(L)F1526 Pinout Description” function. 2011 Microchip Technology Inc. PIC16(L)F1526/ RB0 47 RB1 46 RB2 45 RB3 44 RB4 RB5 43 42 RB6 41 V PIC16(L)F1526 40 RA6 PIC16(L)F1527 RA7 RB7 37 ...
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... Y — — Y — — Y — — Y — — Y — — Y — — Y — — Y — — Y — — Y — — Y — — Y — — Y — — Y — — Y — 2011 Microchip Technology Inc. ...
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... SS Note 1: Peripheral pin location selected using APFCON register. Default Location. 2: Peripheral pin location selected using APFCON register. Alternate Location. 3: Weak pull-up is always enabled when MCLR is enabled, otherwise the pull-up is under user control. 2011 Microchip Technology Inc. PIC16(L)F1526/27 (2) CCP2 — ...
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... Development Support............................................................................................................................................................... 333 28.0 Packaging Information.............................................................................................................................................................. 335 Appendix A: Revision History............................................................................................................................................................. 343 Index .................................................................................................................................................................................................. 345 The Microchip Web Site ..................................................................................................................................................................... 351 Customer Change Notification Service .............................................................................................................................................. 351 Customer Support .............................................................................................................................................................................. 351 Reader Response .............................................................................................................................................................................. 352 Product Identification System............................................................................................................................................................. 353 DS41458B-page 8 ) ................................................................................................................................ 283 ™ Preliminary 2011 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com 2011 Microchip Technology Inc. PIC16(L)F1526/27 to receive the most current information on all of our products. Preliminary DS41458B-page 9 ...
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... PIC16(L)F1526/27 NOTES: DS41458B-page 10 Preliminary 2011 Microchip Technology Inc. ...
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... CCP6 CCP7 CCP8 CCP9 CCP10 EUSARTs EUSART1 EUSART2 Master Synchronous Serial Ports MSSP1 MSSP2 Timers Timer0 Timer1/3/5 Timer2/4/6 /8/10 2011 Microchip Technology Inc. PIC16(L)F1526/27 Figure 1-1 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ...
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... See applicable chapters for more information on peripherals. Note 1: See Table 1-1 for peripherals available on specific devices. 2: DS41458B-page 12 Program Flash Memory CPU (Figure 2-1) EUSARTs Timer1/3/5 Timer2/4/6/8/10 Temp. ADC MSSPs Indicator 10-Bit Preliminary PORTA RAM PORTB PORTC PORTD PORTE PORTF PORTG FVR 2011 Microchip Technology Inc. ...
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... XTAL = Crystal Peripheral pin location selected using APFCON register. Default location. Note 1: Peripheral pin location selected using APFCON register. Alternate location. 2: RC3, RC4, RD5 and RD6 read the I 3: 2011 Microchip Technology Inc. PIC16(L)F1526/27 Input Output Type Type TTL CMOS General purpose I/O. ...
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... CMOS General purpose I/O with WPU. ST — SPI data input C™ data input/output. = Schmitt Trigger input with CMOS levels input when I C mode is enabled. Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2011 Microchip Technology Inc. ...
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... XTAL = Crystal Peripheral pin location selected using APFCON register. Default location. Note 1: Peripheral pin location selected using APFCON register. Alternate location. 2: RC3, RC4, RD5 and RD6 read the I 3: 2011 Microchip Technology Inc. PIC16(L)F1526/27 Input Output Type Type ST CMOS General purpose I/O with WPU. ...
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... Power — Analog ground reference. Power — Positive supply. Power — Ground reference. = Schmitt Trigger input with CMOS levels input when I C mode is enabled. Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2011 Microchip Technology Inc. ...
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... Section 3.5 “Indirect Addressing” 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 24.0 “Instruction Set Summary” details. 2011 Microchip Technology Inc. PIC16(L)F1526/27 Saving”, for more details. for more Preliminary DS41458B-page 17 ...
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... Power-up Timer Oscillator Start-up Timer ALU ALU ALU Power- Reset Watchdog W Reg Timer Brown-out Reset Preliminary RAM Addr 12 Indirect Addr 12 FSR0 Reg FSR reg FSR reg STATUS Reg STATUS reg STATUS reg MUX MUX MUX 2011 Microchip Technology Inc. ...
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... Indirect Addressing TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC16F1526 PIC16LF1526 PIC16F1527 PIC16LF1527 2011 Microchip Technology Inc. PIC16(L)F1526/27 3.1 Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. implemented Accessing a location above these boundaries will cause a wrap-around within the implemented memory space ...
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... PIC16(L)F1527 PC<14:0> 15 Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 0FFFh 1000h Page 2 17FFh 1800h Page 3 1FFFh Page 4 2000h Page 7 3FFFh 4000h Rollover to Page 0 Rollover to Page 7 7FFFh 2011 Microchip Technology Inc. ...
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... FSR require one extra instruction cycle to complete. Example 3-2 demonstrates access- ing the program memory via an FSR. The HIGH directive will set bit<7> label points to a location in program memory. 2011 Microchip Technology Inc. PIC16(L)F1526/27 EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR constants RETLW DATA0 ...
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... Preliminary Table 3-2. For detailed 3-4. BANKx INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON 2011 Microchip Technology Inc. ...
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... For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the Note 1: second operand. 2011 Microchip Technology Inc. PIC16(L)F1526/27 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register 3-1, contains: as ‘ ...
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... DEVICE MEMORY MAPS The memory maps for PIC16(L)F1526/27 is shown in Table 3-3. Preliminary BANKED MEMORY PARTITIONING Memory Region Core Registers (12 bytes) Special Function Registers (20 bytes maximum) General Purpose RAM (80 bytes maximum) Common RAM (16 bytes) 2011 Microchip Technology Inc. ...
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TABLE 3-3: PIC16(L)F1526/27 MEMORY MAP BANK 0 BANK 1 000h 080h 100h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 00Bh 08Bh 10Bh 00Ch PORTA 08Ch TRISA 10Ch 00Dh PORTB 08Dh TRISB 10Dh 00Eh PORTC 08Eh TRISC 10Eh ...
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TABLE 3-3: PIC16(L)F1526/27 MEMORY MAP (CONTINUED) BANK 8 BANK 9 400h 480h 500h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 40Bh 48Bh 50Bh ANSELF — 40Ch 48Ch 50Ch ANSELG WPUG 40Dh 48Dh — — 40Eh 48Eh — ...
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TABLE 3-3: PIC16(L)F1526/27 MEMORY MAP (CONTINUED) BANK 16 BANK 17 800h 880h 900h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 80Bh 88Bh 90Bh 80Ch 88Ch 90Ch Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ 81Fh 89Fh ...
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TABLE 3-3: PIC16(L)F1526 MEMORY MAP (CONTINUED) Bank 31 F80h Core Registers (Table 3-2) F8Bh F8Ch Unimplemented Read as ‘0’ FE3h STATUS_SHAD FE4h WREG_SHAD FE5h BSR_SHAD FE6h PCLATH_SHAD FE7h FSR0L_SHAD FE8h FSR0H_SHAD FE9h FSR1L_SHAD FEAh FSR1H_SHAD FEBh — FECh FEDh STKPTR ...
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... Write Buffer for the upper 7 bits of the Program Counter x8Ah x0Bh or INTCON GIE PEIE x8Bh x = unknown unchanged value depends on condition unimplemented, read as ‘0’ reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 2011 Microchip Technology Inc. PIC16(L)F1526/27 can be Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... SWDTEN --01 0110 --01 0110 — — SCS<1:0> -011 1-00 -011 1-00 LFIOFR HFIOFS 0-q0 --00 q-qq --0q xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu GO/DONE ADON -000 0000 -000 0000 ADPREF<1:0> 0000 --00 0000 --00 — — 2011 Microchip Technology Inc. ...
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... ABDOVF RCIDL Legend unknown unchanged value depends on condition unimplemented, read as ‘0’ reserved. Shaded locations are unimplemented, read as ‘0’. PIC16F1526/7 only. Note 1: Unimplemented, read as ‘1’. 2: 2011 Microchip Technology Inc. PIC16(L)F1526/27 Bit 5 Bit 4 Bit 3 Bit 2 — — — — ...
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... C1TSEL<1:0> 0000 0000 0000 0000 C5TSEL<1:0> 0000 0000 0000 0000 C9TSEL<1:0> ---- 0000 ---- 0000 2011 Microchip Technology Inc. ...
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... Unimplemented 39Fh Legend unknown unchanged value depends on condition unimplemented, read as ‘0’ reserved. Shaded locations are unimplemented, read as ‘0’. PIC16F1526/7 only. Note 1: Unimplemented, read as ‘1’. 2: 2011 Microchip Technology Inc. PIC16(L)F1526/27 Bit 5 Bit 4 Bit 3 Bit 2 TRISF5 TRISF4 TRISF3 TRISF2 — ...
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... OERR RX9D 0000 000x 0000 000x TRMT TX9D 0000 0010 0000 0010 WUE ABDEN 01-0 0-00 01-0 0-00 — — 2011 Microchip Technology Inc. ...
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... Legend unknown unchanged value depends on condition unimplemented, read as ‘0’ reserved. Shaded locations are unimplemented, read as ‘0’. PIC16F1526/7 only. Note 1: Unimplemented, read as ‘1’. 2: 2011 Microchip Technology Inc. PIC16(L)F1526/27 Bit 5 Bit 4 Bit 3 Bit 2 T8OUTPS<3:0> TMR8ON T10OUTPS<3:0> TMR10ON DC6B<1:0> ...
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... Microchip Technology Inc. ...
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... GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, “Implementing a Table Read” (DS00556). 2011 Microchip Technology Inc. PIC16(L)F1526/27 3.3.3 COMPUTED FUNCTION CALLS A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables ...
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... Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will 0x05 return the contents of stack address 0x0F. 0x04 0x03 0x02 0x01 0x00 0x1F 0x0000 STKPTR = 0x1F Preliminary 3-5 through 3-8 for examples of Stack Reset Disabled (STVREN = 0) Stack Reset Enabled (STVREN = 1) 2011 Microchip Technology Inc. ...
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... FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 TOSH:TOSL FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3 TOSH:TOSL 2011 Microchip Technology Inc. PIC16(L)F1526/27 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. 0x08 ...
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... Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will 0x06 Return Address not be overwritten. 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address STKPTR = 0x10 Preliminary 2011 Microchip Technology Inc. ...
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... FIGURE 3-9: INDIRECT ADDRESSING FSR Address Range Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: 2011 Microchip Technology Inc. PIC16(L)F1526/27 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory ...
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... FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 00000 00001 00010 0x00 0x7F Bank 0 Bank 1 Bank 2 DS41458A-page 42 Indirect Addressing 0 7 FSRxH Bank Select 11111 Bank 31 Preliminary 7 FSRxL 0 Location Select 2011 Microchip Technology Inc. ...
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... FSRnL Location Select 0x2000 0x29AF 2011 Microchip Technology Inc. PIC16(L)F1526/27 3.5.3 PROGRAM FLASH MEMORY To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF ...
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... PIC16(L)F1526/27 NOTES: DS41458A-page 44 Preliminary 2011 Microchip Technology Inc. ...
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... These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. The DEBUG bit in Configuration Word 2 is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. 2011 Microchip Technology Inc. PIC16(L)F1526/27 by device Preliminary DS41458B-page 45 ...
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... WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled DS41458B-page 46 R/P-1 R/P-1 R/P-1 IESO CLKOUTEN BOREN<1:0> R/P-1 R/P-1 R/P-1 WDTE<1:0> Unimplemented bit, read as ‘1’ Value when blank or after Bulk Erase Preliminary R/P-1 U-1 — bit 8 R/P-1 R/P-1 FOSC<2:0> bit 0 2011 Microchip Technology Inc. ...
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... EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins 000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins 2011 Microchip Technology Inc. PIC16(L)F1526/27 Preliminary DS41458B-page 47 ...
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... R/P-1 DEBUG LPBOR BORV R/P-1 U-1 U-1 (1) VCAPEN — — Unimplemented bit, read as ‘1’ Value when blank or after Bulk Erase (1) pin functions are disabled. CAP Preliminary R/P-1 U-1 STVREN — bit 8 R/P-1 R/P-1 WRT<1:0> bit 0 2011 Microchip Technology Inc. ...
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... See Section 11.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16F/LF151X/152X Memory Programming Specification” (DS41422). 2011 Microchip Technology Inc. PIC16(L)F1526/27 “Write such as Preliminary ...
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... These bits are used to identify the revision (see Table under DEV<8:0> above). DS41458B-page DEV<8:3> REV<4:0> Unimplemented bit, read as ‘1’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit DEVICEID<13:0> Values DEV<8:0> REV<4:0> x xxxx x xxxx x xxxx x xxxx Preliminary bit bit 0 2011 Microchip Technology Inc. ...
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... Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources • Fast start-up oscillator allows internal circuits to power up and stabilize before switching to the 16 MHz HFINTOSC 2011 Microchip Technology Inc. PIC16(L)F1526/27 The oscillator module can be configured in one of eight clock modes. 1. ECL – External Clock Low Power mode (0 MHz to 0 ...
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... HF-500 kHz 1010/ /32 0111 HF-250 kHz 1001/ /64 0110 HF-125 kHz 1000/ /128 0101 HF-62.5 kHz /256 0100 HF-31.25 kHz 0011 /512 0010 LF-31 kHz 0001 0000 Preliminary Low Power Mode Event Switch (SCS<1:0>) 2 Primary Clock 00 01 INTOSC 1x 2011 Microchip Technology Inc. ...
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... Configuration Word 1: • High power, 4-20 MHz (FOSC = 111) • Medium power, 0.5-4 MHz (FOSC = 110) • Low power, 0-0.5 MHz (FOSC = 101) 2011 Microchip Technology Inc. PIC16(L)F1526/27 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...
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... Start-up mode can be selected (see “Two-Speed Clock Start-up Preliminary CERAMIC RESONATOR OPERATION ( MODE) ® PIC MCU OSC1/CLKIN To Internal Logic R (3) ( Sleep F OSC2/CLKOUT R S (1) ) may be required for S varies with the Oscillator mode F P Oscillator Start-up Timer (OST) Section 5.4 Mode”). 2011 Microchip Technology Inc. ) ...
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... MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288) 2011 Microchip Technology Inc. PIC16(L)F1526/27 5.2.1.5 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required ...
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... Watchdog Timer (WDT) Internal • Fail-Safe Clock Monitor (FSCM) The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized. Preliminary Figure 5-1). Select 31 kHz, via for more information. The 2011 Microchip Technology Inc. ...
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... Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transi- tion times can be obtained between frequency changes that use the same oscillator source. 2011 Microchip Technology Inc. PIC16(L)F1526/27 5.2.2.4 Internal Oscillator Clock Switch Timing ...
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... System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time HFINTOSC IRCF <3:0> System Clock DS41458B-page 58 Start-up Time 2-cycle Sync 0 2-cycle Sync LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync 0 Preliminary Running Running Running 2011 Microchip Technology Inc. ...
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... Word 1, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP modes. The OST does not reflect the status of the secondary oscillator. 2011 Microchip Technology Inc. PIC16(L)F1526/27 5.3.3 SECONDARY OSCILLATOR The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral ...
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... Oscillator Delay 31 kHz Oscillator Warm-up Delay (T 31.25 kHz-16 MHz DC – 20 MHz 2 cycles DC – 20 MHz 1 cycle of each 32 kHz-20 MHz 1024 Clock Cycles (OST) 2 s (approx.) 31.25 kHz-16 MHz 31 kHz 1 cycle of each 1024 Clock Cycles (OST) Preliminary 2011 Microchip Technology Inc. ) WARM ...
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... OSC1 1022 1023 0 1 OSC2 Program Counter System Clock 2011 Microchip Technology Inc. PIC16(L)F1526/27 5.4.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC< ...
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... Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed. Preliminary 2011 Microchip Technology Inc. ...
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... Clock Output Clock Monitor Output (Q) OSCFIF The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in Note: this example have been chosen for clarity. 2011 Microchip Technology Inc. PIC16(L)F1526/27 Oscillator Failure Test Test Preliminary Failure ...
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... Secondary oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1. Duplicate frequency derived from HFINTOSC. Note 1: DS41458B-page 64 R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary U-0 R/W-0/0 R/W-0/0 SCS<1:0> — bit 0 2011 Microchip Technology Inc. ...
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... CONFIG1 7:0 CP MCLRE — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. Legend: 2011 Microchip Technology Inc. PIC16(L)F1526/27 R-0/q U-0 HFIOFR — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
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... PIC16(L)F1526/27 NOTES: DS41458B-page 66 Preliminary 2011 Microchip Technology Inc. ...
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... External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset LPBOR Reset BOR Enable 2011 Microchip Technology Inc. PIC16(L)F1526/27 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 6-1. PWRT Zero 64 ms LFINTOSC PWRTEN Preliminary Device Reset DS41458B-page 67 ...
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... V for a DD BOR , the device BORDC Figure 6-2 for more information. Device Operation upon wake- up from Sleep (1) Waits for BOR ready Waits for BOR ready Begins immediately Begins immediately Begins immediately level. DD 2011 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive BOREN<1:0> bits are located in Configuration Word 1. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1526/27 (1) T PWRT < T PWRT PWRT (1) ...
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... Upon bringing MCLR high, the device will begin execution immediately (see is useful for testing purposes or to synchronize more than one device operating in parallel. Preliminary Table 6-4 Section 3.4.2 “Overflow/Underflow Timer configuration. See Figure 6-3). This 2011 Microchip Technology Inc. ...
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... FIGURE 6-3: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2011 Microchip Technology Inc. PIC16(L)F1526/27 T PWRT T MCLR T OST Preliminary DS41458B-page 71 ...
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... ---0 0uuu 0000h ---1 1uuu ( ---1 0uuu 0000h ---u uuuu 0000h ---u uuuu 0000h ---u uuuu Preliminary Condition PCON Register 00-1 110x uu-u 0uuu uu-u 0uuu uu-0 uuuu uu-u uuuu 00-1 11u0 uu-u uuuu uu-u u0uu 1u-u uuuu u1-u uuuu 2011 Microchip Technology Inc. ...
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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2011 Microchip Technology Inc. PIC16(L)F1526/27 6-2. R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q RWDT ...
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... Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets. DS41458B-page 74 Bit 5 Bit 4 Bit 3 Bit 2 — — — — — RMCLR RI RWDT — WDTPS<4:0> Preliminary Register Bit 1 Bit 0 on Page — BORRDY 69 POR BOR SWDTEN 99 2011 Microchip Technology Inc. ...
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... Many peripherals produce Interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure 7-1. FIGURE 7-1: INTERRUPT LOGIC Peripheral Interrupts (TMR1IF) PIR1<0> (TMR1IF) PIR1<0> PIRn<7> PIEn<7> 2011 Microchip Technology Inc. PIC16(L)F1526/27 TMR0IF TMR0IE INTF INTE IOCIF IOCIE PEIE GIE Preliminary Wake-up ...
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... The latency for synchronous interrupts instruction cycles. For asynchronous interrupts, the latency instruction cycles, depending on when the interrupt occurs. See and Figure 7-3 for more details. Preliminary 2011 Microchip Technology Inc. Figure 7-2 ...
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... PC PC Execute 2 Cycle Instruction at PC Interrupt GIE PC Execute 3 Cycle Instruction at PC Interrupt GIE PC Execute 3 Cycle Instruction at PC 2011 Microchip Technology Inc. PIC16(L)F1526/27 Interrupt Sampled during Q1 PC+1 0004h Inst(PC) NOP NOP PC+1/FSR New PC/ 0004h ADDR PC+1 Inst(PC) NOP NOP FSR ADDR ...
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... INTF is enabled to be set any time during the Q4-Q1 cycles. DS41458B-page (1) (2) Interrupt Latency Inst ( — Dummy Cycle Dummy Cycle Inst (PC) . Synchronous latency = 3 Section 25.0 “Electrical Preliminary 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) , where T = instruction cycle time Specifications”. 2011 Microchip Technology Inc. ...
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... ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved. 2011 Microchip Technology Inc. PIC16(L)F1526/27 Section 8.0 Preliminary DS41458B-page 79 ...
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... User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. R/W-0/0 R/W-0/0 R/W-0/0 INTE IOCIE TMR0IF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-0/0 R-0/0 INTF IOCIF bit 0 2011 Microchip Technology Inc. ...
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... Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt 2011 Microchip Technology Inc. PIC16(L)F1526/27 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. ...
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... Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. U-0 R/W-0/0 R/W-0/0 — BCL1IE TMR10IE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary 2011 Microchip Technology Inc. R/W-0/0 R/W-0/0 TMR8IE CCP2IE bit 0 ...
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... Disables the TMR4 to PR4 Match interrupt bit 0 TMR3IE: Timer3 Overflow Interrupt Enable bit 1 = Enables the Timer3 overflow interrupt 0 = Disables the Timer3 overflow interrupt 2011 Microchip Technology Inc. PIC16(L)F1526/27 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. ...
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... Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R-0/0 R/W-0/0 R/W-0/0 TX2IE CCP8IE CCP7IE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 BCL2IE SSP2IE bit 0 2011 Microchip Technology Inc. ...
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... Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending 2011 Microchip Technology Inc. PIC16(L)F1526/27 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...
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... U-0 R/W-0/0 R/W-0/0 — BCL1IF TMR10IF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary 2011 Microchip Technology Inc. should ensure the R/W-0/0 R/W-0/0 TMR8IF CCP2IF bit 0 ...
Page 87
... Interrupt is pending 0 = Interrupt is not pending bit 0 TMR3IF: Timer3 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending 2011 Microchip Technology Inc. PIC16(L)F1526/27 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...
Page 88
... R-0/0 R/W-0/0 R/W-0/0 TX2IF CCP8IF CCP7IF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary should ensure the R/W-0/0 R/W-0/0 BCL2IF SSP2IF bit 0 2011 Microchip Technology Inc. ...
Page 89
... TMR1GIF ADIF PIR2 OSFIF TMR5GIF PIR3 CCP6IF CCP5IF PIR4 CCP10IF CCP9IF — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts. Legend: 2011 Microchip Technology Inc. PIC16(L)F1526/27 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF IOCBF5 IOCBF4 IOCBF3 ...
Page 90
... PIC16(L)F1526/27 NOTES: DS41458B-page 90 Preliminary 2011 Microchip Technology Inc. ...
Page 91
... See Section 8.0 “Digital-to-Analog Con- verter (DAC) Module” and Section 14.0 “Fixed Volt- for more information on these age Reference (FVR)” modules. 2011 Microchip Technology Inc. PIC16(L)F1526/27 8.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1 ...
Page 92
... SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP (3) T OST Interrupt Latency (4) Processor in Sleep Inst( Inst( Dummy Cycle Preliminary 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) 2011 Microchip Technology Inc. ...
Page 93
... The Low-Power Sleep mode is beneficial for applica- tions that stay in Sleep mode for long periods of time. The normal mode is beneficial for applications that need to wake from Sleep quickly and frequently. 2011 Microchip Technology Inc. PIC16(L)F1526/27 8.2.2 PERIPHERAL USAGE IN SLEEP Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected ...
Page 94
... Reserved bit 0 Register on Bit 1 Bit 0 Page INTF IOCIF 80 IOCBF1 IOCBF0 143 IOCBN1 IOCBN0 143 IOCBP1 IOCBP0 143 TMR2IE TMR1IE 81 TMR8IE CCP2IE 82 TMR4IE TMR3IE 83 BCL2IE SSP2IE 84 TMR2IF TMR1IF 85 TMR8IF CCP2IF 86 TMR4IF TMR3IF 87 BCL2IF SSP2IF VREGPM 94 Reserved SWDTEN 99 2011 Microchip Technology Inc. ...
Page 95
... Shaded cells are not used by LDO. Legend: PIC16F1526/27 only. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1526/27 On power-up, the external capacitor will load the LDO voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source charges the external capacitor ...
Page 96
... PIC16(L)F1526/27 NOTES: DS41458B-page 96 Preliminary 2011 Microchip Technology Inc. ...
Page 97
... Configurable time-out period is from 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2011 Microchip Technology Inc. PIC16(L)F1526/27 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41458B-page 97 ...
Page 98
... See Section 3.0 “Memory Organization” Mode The STATUS register information. Active Active Disabled Active Disabled Disabled Preliminary Section 5.0 “Oscillator for more and (Register 3-1) for more WDT Cleared Cleared until the end of OST Unaffected 2011 Microchip Technology Inc. ...
Page 99
... WDT is turned WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. Times are approximate. WDT time is based on 31 kHz LFINTOSC. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1526/27 R/W-1/1 R/W-0/0 WDTPS<4:0> Unimplemented bit, read as ‘0’ -m/n = Value at POR and BOR/Value at all other Resets ...
Page 100
... IRCF<3:0> — — WDTPS<4:0> Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 FCMEN IESO CLKOUTEN PWRTE WDTE<1:0> Preliminary Register Bit 1 Bit 0 on Page SCS<1:0> SWDTEN 99 . Watchdog Timer Register Bit 9/1 Bit 8/0 on Page BOREN<1:0> — 46 FOSC<2:0> 2011 Microchip Technology Inc. ...
Page 101
... The PMADRH:PMADRL register pair can address maximum of 32K words of program memory. When selecting a program address value, the MSB of the address is written to the PMADRH register and the LSB is written to the PMADRL register. 2011 Microchip Technology Inc. PIC16(L)F1526/27 11.1.1 PMCON1 AND PMCON2 REGISTERS PMCON1 is the control register for Flash program memory accesses ...
Page 102
... Instruction Fetched ignored the next Preliminary FLASH PROGRAM MEMORY READ FLOWCHART Start Read Operation Select (CFGS) Select Word Address (PMADRH:PMADRL) Initiate Read Operation ( NOP execution forced NOP execution forced Data read now in PMDATH:PMDATL End Read Operation 2011 Microchip Technology Inc. ...
Page 103
... Ignored MOVF PMDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2011 Microchip Technology Inc. PIC16(L)F1526/27 PMADRH,PMADRL PC+3 INSTR ( PMDATH,PMDATL INSTR ( INSTR( INSTR( instruction ignored instruction ignored Forced NOP Forced NOP ...
Page 104
... FIGURE 11-3: FLASH PROGRAM MEMORY UNLOCK SEQUENCE FLOWCHART Start Unlock Sequence Write 055h to PMCON2 Write 0AAh to PMCON2 Initiate Write or Erase Operation ( Instruction Fetched ignored NOP execution forced Instruction Fetched ignored NOP execution forced Unlock Sequence Preliminary 2011 Microchip Technology Inc. End ...
Page 105
... This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the PMCON1 WRITE instruc- tion. 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 11-4: FLASH PROGRAM MEMORY ERASE ...
Page 106
EXAMPLE 11-2: ERASING ONE ROW OF PROGRAM MEMORY ; This row erase routine assumes the following valid address within the erase row is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory ...
Page 107
... Write opera- tions do not cross these boundaries. At the completion of a program memory write operation, the data in the write latches is reset to contain 0x3FFF. 2011 Microchip Technology Inc. PIC16(L)F1526/27 The following steps should be completed to load the write latches and program a row of program memory. ...
Page 108
... DEVICEID USER reserved REVID CFGS = 1 Configuration Memory Preliminary PMDATL Write Latch #30 Write Latch #31 1Eh 1Fh 14 14 Addr Addr 001Eh 001Fh 003Eh 003Fh 005Eh 005Fh 7FDEh 7FDFh 7FFEh 7FFFh 8007h - 8008h 8009h - 801Fh Configuration reserved Words 2011 Microchip Technology Inc. ...
Page 109
... Select Program or Config. Memory (CFGS) Select Row Address (PMADRH:PMADRL) Select Write Operation (FREE = 0) Load Write Latches Only (LWLO = 1) 2011 Microchip Technology Inc. PIC16(L)F1526/27 Enable Write/Erase Operation (WREN = 1) Load the value to write (PMDATH:PMDATL) Update the word counter (word_cnt--) Yes Last word to ...
Page 110
... NOP instructions are forced as processor writes ; all the program memory write latches simultaneously ; to program memory. ; After NOPs, the processor ; stalls until the self-write process in complete ; after write processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary 2011 Microchip Technology Inc. ...
Page 111
... Load the starting address of the row to be rewritten. 5. Erase the program memory row. 6. Load the write latches with data from the RAM image. 7. Initiate a programming operation. 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 11-7: FLASH PROGRAM MEMORY MODIFY FLOWCHART Start Modify Operation Read Operation (Figure x ...
Page 112
... MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location DS41458B-page 112 11-2, the Function Read Access User IDs Yes Yes Yes Figure 11-2) Figure 11-2) Preliminary Write Access Yes No No 2011 Microchip Technology Inc. ...
Page 113
... RAM. This image will be used to verify the data currently stored in Flash Program Memory. Read Operation (Figure x.x) Figure 11-2 PMDAT = No RAM image ? Fail Yes Verify Operation No Last Word ? Yes End Verify Operation 2011 Microchip Technology Inc. PIC16(L)F1526/27 Preliminary DS41458B-page 113 ...
Page 114
... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 PMADR<14:8> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u bit 0 R/W-x/u R/W-x/u bit 0 R/W-0/0 R/W-0/0 bit 0 R/W-0/0 R/W-0/0 bit 0 2011 Microchip Technology Inc. ...
Page 115
... Does not initiate a program Flash read. Unimplemented bit, read as ‘ 1 ’. Note 1: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started ( The LWLO bit is ignored during a program memory erase operation (FREE = 2011 Microchip Technology Inc. PIC16(L)F1526/27 (2) R/W/HC-0/0 R/W/HC-x/q R/W-0/0 FREE ...
Page 116
... VCAPEN — Preliminary W-0/0 W-0/0 W-0/0 bit 0 Register on Bit 1 Bit 0 Page WR RD 115 116 114 114 114 114 INTF IOCIF 80 Register Bit 10/2 Bit 9/1 Bit 8/0 on Page BOREN<1:0> — 46 FOSC<2:0> BORV STVREN — 48 — WRT<1:0> 2011 Microchip Technology Inc. ...
Page 117
... The port has analog functions and has an ANSELA register which can disable the digital input and save power. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 12-1. 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 12-1: D Write LATx Write PORTx ...
Page 118
... CCP2SEL: Pin Selection bit 0 = CCP2 function is on RC1 1 = CCP2 function is on RE7 DS41458B-page 118 U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary 2011 Microchip Technology Inc. R/W-0/0 R/W-0/0 T3CKISEL CCP2SEL bit 0 ...
Page 119
... Note: mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘ 0 ’ by user software. 2011 Microchip Technology Inc. PIC16(L)F1526/27 12.2.2 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The ...
Page 120
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATA4 LATA3 LATA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/x R/W-x/x RA1 RA0 bit 0 R/W-1/1 R/W-1/1 TRISA1 TRISA0 bit 0 R/W-x/u R/W-x/u LATA1 LATA0 bit 0 2011 Microchip Technology Inc. ...
Page 121
... Bit -/6 13:8 — CONFIG1 7:0 CP MCLRE — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA. Legend: 2011 Microchip Technology Inc. PIC16(L)F1526/27 U-0 R/W-1/1 R/W-1/1 — ANSA3 ANSA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) ...
Page 122
... Pin Name RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 Priority listed from highest to lowest. Note 1: Preliminary 12-5. Table 12-5. PORTB OUTPUT PRIORITY (1) Function Priority RB0 RB1 RB2 CCP2 RB3 RB4 RB5 ICDCLK RB6 ICDDAT RB7 2011 Microchip Technology Inc. ...
Page 123
... Bit is cleared bit 7-0 LATB<7:0> : PORTB Output Latch Value bits Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is Note 1: return of actual I/O pin values. 2011 Microchip Technology Inc. PIC16(L)F1526/27 R/W-x/u R/W-x/u R/W-x/u RB4 RB3 RB2 U = Unimplemented bit, read as ‘ ...
Page 124
... R/W-1/1 R/W-1/1 ANSB2 ANSB1 ANSB0 bit 0 R/W-1/1 R/W-1/1 R/W-1/1 WPUB2 WPUB1 WPUB0 bit 0 Register Bit 1 Bit 0 on Page T3CKISEL CCP2SEL 124 ANSB1 ANSB0 124 LATB1 LATB0 123 RB1 RB0 123 TRISB1 TRISB0 123 WPUB1 WPUB0 124 2011 Microchip Technology Inc. ...
Page 125
... The user should ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘ 0 ’. 2011 Microchip Technology Inc. PIC16(L)F1526/27 12.4.1 PORTC FUNCTIONS AND OUTPUT PRIORITIES Each PORTC pin is multiplexed with other functions ...
Page 126
... Value at POR and BOR/Value at all other Resets (1) R/W-x/u R/W-x/u R/W-x/u LATC4 LATC3 LATC2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u RC1 RC0 bit 0 R/W-1/1 R/W-1/1 TRISC1 TRISC0 bit 0 R/W-x/u R/W-x/u LATC1 LATC0 bit 0 2011 Microchip Technology Inc. ...
Page 127
... LATC LATC7 LATC6 PORTC RC7 RC6 TRISC TRISC7 TRISC6 x = unknown unchanged unimplemented locations read as ‘ 0 ’. Shaded cells are not used by PORTC. Legend: 2011 Microchip Technology Inc. PIC16(L)F1526/27 Bit 5 Bit 4 Bit 3 Bit 2 — — — — LATC5 LATC4 LATC3 ...
Page 128
... Priority listed from highest to lowest. Note 1: RD5 and RD6 read the Preliminary Table 12-9. Table 12-9. PORTD OUTPUT PRIORITY (1) Function Priority RD0 RD1 RD2 RD3 SDO2 RD4 SDA2 (2) RD5 SCL2 SCK2 (2) RD6 RD7 input when C mode is enabled. 2011 Microchip Technology Inc. ...
Page 129
... Bit is cleared bit 7-0 LATD<7:0> : PORTD Output Latch Value bits Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is Note 1: return of actual I/O pin values. 2011 Microchip Technology Inc. PIC16(L)F1526/27 R/W-x/u R/W-x/u R/W-x/u RD4 RD3 RD2 U = Unimplemented bit, read as ‘ ...
Page 130
... TRISD2 WPUD5 WPUD4 WPUD3 WPUD2 Preliminary R/W-1 R/W-1 ANSD1 ANSD0 bit 0 R/W-1/1 R/W-1/1 WPUD1 WPUD0 bit 0 Register Bit 1 Bit 0 on Page ANSD1 ANSD0 124 LATD1 LATD0 123 RD1 RD0 123 TRISD1 TRISD0 123 WPUD1 WPUD0 130 2011 Microchip Technology Inc. ...
Page 131
... Note: mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘ 0 ’ by user software. 2011 Microchip Technology Inc. PIC16(L)F1526/27 12.6.2 PORTE FUNCTIONS AND OUTPUT PRIORITIES Each PORTE pin is multiplexed with other functions. The ...
Page 132
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATE4 LATE3 LATE2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u RE1 RE0 bit 0 R/W-1/1 R/W-1/1 TRISE1 TRISE0 bit 0 R/W-x/u R/W-x/u LATE1 LATE0 bit 0 2011 Microchip Technology Inc. ...
Page 133
... RE6 TRISE TRISE7 TRISE6 WPUE WPUE7 WPUE6 x = unknown unchanged unimplemented locations read as ‘ 0 ’. Shaded cells are not used by PORTE. Legend: 2011 Microchip Technology Inc. PIC16(L)F1526/27 U-0 U-0 R/W-1 ANSE2 — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) ...
Page 134
... TABLE 12-13: PORTF OUTPUT PRIORITY Pin Name RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 Priority listed from highest to lowest. Note 1: PIC16F1526/27 only 2: Preliminary Table 12-13. Table 12-13. (1) Function Priority (2) V CAP RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 2011 Microchip Technology Inc. ...
Page 135
... Bit is cleared bit 7-0 LATF<7:0> : PORTF Output Latch Value bits Writes to PORTF are actually written to corresponding LATF register. Reads from PORTF register is return Note 1: of actual I/O pin values. 2011 Microchip Technology Inc. PIC16(L)F1526/27 R/W-x/u R/W-x/u R/W-x/u RF4 ...
Page 136
... VCAPEN — Preliminary R/W-1 R/W-1 ANSF1 ANSF0 bit 0 Register Bit 1 Bit 0 on Page ANSF1 ANSF0 136 LATF1 LATF0 135 RF1 RF0 135 TRISF1 TRISF0 135 Register Bit 9/1 Bit 8/0 on Page STVREN — 48 — WRT<1:0> 2011 Microchip Technology Inc. ...
Page 137
... Note: mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘ 0 ’ by user software. 2011 Microchip Technology Inc. PIC16(L)F1526/27 12.8.2 PORTG FUNCTIONS AND OUTPUT PRIORITIES Each PORTG pin is multiplexed with other functions. The ...
Page 138
... Value at POR and BOR/Value at all other Resets (1) (1) R/W-1 R/W-1 TRISG4 TRISG3 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u R/W-x/u RG2 RG1 RG0 bit 0 R/W-1 R/W-1 R/W-1 TRISG2 TRISG1 TRISG0 bit 0 2011 Microchip Technology Inc. ...
Page 139
... Analog input. Pin is assigned as analog input bit 0 Unimplemented: Read as ‘ 0 ’ When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin. 2011 Microchip Technology Inc. PIC16(L)F1526/27 R/W-x/u R/W-x/u R/W-x/u LATG4 ...
Page 140
... U-0 U-0 U-0 — — — bit 0 Register Bit 1 Bit 0 on Page ANSG1 — 139 LATG1 LATG0 139 RG1 RG0 138 TRISG1 TRISG0 138 — — 140 Register Bit 9/1 Bit 8/0 on Page BOREN<1:0> — 48 FOSC<2:0> 2011 Microchip Technology Inc. ...
Page 141
... A pin can be configured to detect rising and falling edges simultaneously by setting both the IOCBPx bit and the IOCBNx bit of the IOCBP and IOCBN registers, respectively. 2011 Microchip Technology Inc. PIC16(L)F1526/27 13.3 Interrupt Flags The IOCBFx bits located in the IOCBF register are status flags that correspond to the Interrupt-on-change pins of PORTB ...
Page 142
... INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCBNx RBx IOCBPx Q4Q1 Q4Q1 DS41458B-page 142 Q4Q1 edge detect data bus = write IOCBFx CK from all other IOCBFx individual pin detectors Q4Q1 Preliminary to data bus IOCBFx IOCIE IOC interrupt to CPU core Q3 Q4 Q4Q1 2011 Microchip Technology Inc. ...
Page 143
... An enabled change was detected on the associated pin. Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling edge was detected on RBx change was detected, or the user cleared the detected change. 2011 Microchip Technology Inc. PIC16(L)F1526/27 R/W-0/0 R/W-0/0 ...
Page 144
... IOCBP2 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBF5 IOCBF4 IOCBF3 IOCBF2 TRISB5 TRISB4 TRISB3 TRISB2 Preliminary Register Bit 1 Bit 0 on Page ANSB1 ANSB0 124 INTF IOCIF 80 IOCBP1 IOCBP0 143 IOCBN1 IOCBN0 143 IOCBF1 IOCBF0 143 TRISB1 TRISB0 123 2011 Microchip Technology Inc. ...
Page 145
... BOR BOREN<1:0> and BORFS = 1 BOREN<1:0> and BORFS = 1 LDO All PIC16F1526/27 devices, when VREGPM = 1 and not in Sleep 2011 Microchip Technology Inc. PIC16(L)F1526/27 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC module is routed through two independent programmable gain amplifiers. Each amplifier can be configured to amplify , with 1 ...
Page 146
... Value at POR and BOR/Value at all other Resets q = Value depends on condition (1) (Low Range) (High Range Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG — — Preliminary U-0 R/W-0/0 R/W-0/0 ADFVR<1:0> — bit 0 (2) (2) Register Bit 1 Bit 0 on page ADFVR<1:0> 146 2011 Microchip Technology Inc. ...
Page 147
... The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 15-1: 15.2 Minimum Operating V ...
Page 148
... PIC16(L)F1526/27 NOTES: DS41458B-page 148 Preliminary 2011 Microchip Technology Inc. ...
Page 149
... Temp Indicator FVR Buffer1 CHS<4:0> When ADON = 0, all multiplexer inputs are disconnected. Note 1: See ADCON0 register 2: 2011 Microchip Technology Inc. PIC16(L)F1526/27 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. (ADC) allows ...
Page 150
... Unless using the F Note: system clock frequency will change the ADC adversely affect the ADC result. Section 16.2 Preliminary peri- AD Figure 16-2. specifica- AD for Table 16-1 gives examples of appro- , any changes in the RC clock frequency, which may 2011 Microchip Technology Inc. ...
Page 151
... Sleep mode. FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 2011 Microchip Technology Inc. PIC16(L)F1526/ DEVICE OPERATING FREQUENCIES AD S Device Frequency (F 16 MHz 8 MHz (2) 125 ns (2) 250 ns (2) (2) 250 ns 500 ns (2) 0.5 s (2) 1.0 ...
Page 152
... ADCON1 register controls the output format. Figure 16-3 shows the two output formats. ADRESH LSB bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result Preliminary ADRESL bit 0 Unimplemented: Read as ‘ 0 ’ LSB bit 0 2011 Microchip Technology Inc. ...
Page 153
... A device Reset forces all registers to their Note: Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2011 Microchip Technology Inc. PIC16(L)F1526/27 16.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...
Page 154
... MOVF ADRESL,W MOVWF RESULTLO Preliminary A/D CONVERSION ; ;clock ;Vdd and Vss Vref ; ;Set RA0 to input ; ;Set RA0 to analog ; ;Turn ADC On ;Acquisiton delay ;No, test again ; ;Read upper 2 bits ;store in GPR space ; ;Read lower 8 bits ;Store in GPR space 2011 Microchip Technology Inc. ...
Page 155
... ADC is disabled and consumes no operating current See Note 1: Section 14.0 “Fixed Voltage Reference (FVR)” See 2: Section 15.0 “Temperature Indicator Module” 2011 Microchip Technology Inc. PIC16(L)F1526/27 R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (2) ...
Page 156
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets DD (1) pin REF + pin as the source of the positive reference, be aware that a REF Section 25.0 “Electrical Specifications” Preliminary R/W-0/0 R/W-0/0 ADPREF<1:0> bit 0 (1) for details. 2011 Microchip Technology Inc. ...
Page 157
... Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0> : ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved : Do not use. 2011 Microchip Technology Inc. PIC16(L)F1526/27 R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 158
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u ADRES<9:8> bit 0 R/W-x/u R/W-x/u bit 0 2011 Microchip Technology Inc. ...
Page 159
... REF 2: The charge holding capacitor (C 3: The maximum recommended impedance for analog sources . This is required to meet the pin leakage specification. 2011 Microchip Technology Inc. PIC16(L)F1526/27 source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...
Page 160
... V - REF DS41458B-page 160 V DD Sampling Switch 0. Rss R IC LEAKAGE (1) I 0. Full-Scale Range 0.5 LSB Zero-Scale Full-Scale Transition V REF Transition Preliminary HOLD REF Sampling Switch (k ) Analog Input Voltage 1.5 LSB + 2011 Microchip Technology Inc. ...
Page 161
... TRISD6 TRISE TRISE7 TRISE6 TRISF TRISF7 TRISF6 TRISG — — — = unimplemented read as ‘ 0 ’. Shaded cells are not used for ADC module. Legend: 2011 Microchip Technology Inc. PIC16(L)F1526/27 Bit 5 Bit 4 Bit 3 Bit 2 CHS<4:0> — — — ANSA4 — ANSA2 ...
Page 162
... PIC16(L)F1526/27 NOTES: DS41458B-page 162 Preliminary 2011 Microchip Technology Inc. ...
Page 163
... OSC 0 T0CKI 1 TMR0SE TMR0CS 2011 Microchip Technology Inc. PIC16(L)F1526/27 17.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on either the rising or falling edge of the T0CKI pin. The edge that increments the counter is determined by the TMR0SE bit in the OPTION_REG register ...
Page 164
... Section 25.0 “Electrical . Specifications” 17.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41458B-page 164 Preliminary 2011 Microchip Technology Inc. ...
Page 165
... Timer0 Module Register TRISA TRISA7 TRISA6 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. 2011 Microchip Technology Inc. PIC16(L)F1526/27 R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U = Unimplemented bit, read as ‘0’ ...
Page 166
... PIC16(L)F1526/27 NOTES: DS41458B-page 166 Preliminary 2011 Microchip Technology Inc. ...
Page 167
... Timer1 register increments on rising edge. 2: Synchronize does not operate while in Sleep. 3: See Table 18-4 for Timer selection. 4: 2011 Microchip Technology Inc. PIC16(L)F1526/27 • Gate Toggle mode • Gate Single-pulse mode • Gate Value Status • Gate Event Interrupt Figure 18 block diagram of the Timer1/3/5 module. ...
Page 168
... Note 1: ST Buffer is high-speed type when using TxCKI. DS41458B-page 168 (1) 0 OUT 1 Secondary Oscillator Timer (1) 0 Timer 3 1 (1) 0 Timer 5 Preliminary To Clock Switching (SOSC users) TMR1CS<1:0> 10 LFINTOSC 11 Timer1 F /4 OSC 00 FOSC 01 TMR3CS<1:0> 10 LFINTOSC 11 Timer3 F /4 OSC 00 FOSC 01 TMR5CS<1:0> 10 LFINTOSC 11 Timer5 OSC FOSC 01 2011 Microchip Technology Inc. ...
Page 169
... TMRxCS<1:0> SOSCEN 2011 Microchip Technology Inc. PIC16(L)F1526/27 18.2 Clock Source Selection The TMRxCS<1:0> and SOSCEN bits of the TxCON register are used to select the clock source for Timer1/3/5. Table 18-2 selections. 18.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected the ...
Page 170
... Timer1/3/5 will hold the current count. See Figure 18-4 for timing details. TABLE 18-3: TxCLK TxGPOL Preliminary TIMER1/3/5 GATE ENABLE SELECTIONS Timer1/3/5 TxG Operation Counts 0 0 Holds Count 0 1 Holds Count 1 0 Counts 1 1 2011 Microchip Technology Inc. ...
Page 171
... Enabling Toggle mode at the same time Note: as changing the gate polarity may result in indeterminate operation. 2011 Microchip Technology Inc. PIC16(L)F1526/27 Timer3 Gate Source T3G Pin T5G Pin Overflow of Timer0 (TMR0 increments from FFh to 00h) ...
Page 172
... In the event that a write to TMRxH or TMRxL coincides with a Special Event Trigger from the CCP, the write will take precedence. For more information, see . Event Trigger” Preliminary 2011 Microchip Technology Inc. see Section 20.0 . period register for /4 should OSC ...
Page 173
... Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. FIGURE 18-4: TIMER1/3/5 GATE ENABLE MODE TMRxGE TxGPOL TxG_IN TxCKI TxGVAL Timer1/3/5 N 2011 Microchip Technology Inc. PIC16(L)F1526/ Preliminary DS41458B-page 173 ...
Page 174
... TIMER1/3/5 GATE SINGLE-PULSE MODE TMRxGE TxGPOL TxGSPM TxGGO/ Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL Timer1/3/5 N Cleared by software TMRxGIF DS41458B-page 174 Cleared by hardware on falling edge of TxGVAL Set by hardware on falling edge of TxGVAL Preliminary 2011 Microchip Technology Inc Cleared by software ...
Page 175
... TMRxGE TxGPOL TxGSPM TxGTM TxGGO/ Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL Timer1/3/5 N Cleared by software TMRxGIF 2011 Microchip Technology Inc. PIC16(L)F1526/ Set by hardware on falling edge of TxGVAL Preliminary Cleared by hardware on falling edge of TxGVAL Cleared by software DS41458B-page 175 ...
Page 176
... Enables Timer1/3 Stops Timer1/3/5 Clears Timer1/3/5 gate flip-flop DS41458B-page 176 R/W-0/u R/W-0/u R/W-0/u SOSCEN TxSYNC U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ) OSC /4) OSC ) OSC Preliminary U-0 R/W-0/u — TMRxON bit 0 2011 Microchip Technology Inc. ...
Page 177
... TxGSS<1:0>: Timer1/3/5 Gate Source Select bits 00 = Timer1/3/5 gate pin 01 = Timer0 overflow output 10 = Timer2/4/6/8 match PR2/PR4/PR6/PR8 11 = Timer10 match PR10 See Table 18-4 for Timer selection. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1526/27 R/W-0/u R/W/HC-0/u R-x/x TxGSPM TxGGO/ TxGVAL DONE U = Unimplemented bit, read as ‘0’ ...
Page 178
... TMR2IE TMR1IE 81 TMR8IE CCP2IE 82 TMR4IE TMR3IE 83 TMR2IF TMR1IF 85 TMR8IF CCP2IF 86 TMR4IF TMR3IF 87 172* 172* 172* 172* 172* 172* TRISA1 TRISA0 120 — TMR1ON 176 — TMR3ON 176 — TMR5ON 176 T1GSS<1:0> 177 T3GSS<1:0> 177 T5GSS<1:0> 177 2011 Microchip Technology Inc. ...
Page 179
... See Figure 19-1 for a block Timer2/4/6/8/10. FIGURE 19-1: TIMER2/4/6/8/10 BLOCK DIAGRAM Prescaler F /4 OSC 1:1, 1:4, 1:16, 1:64 2 TxCKPS<1:0> 2011 Microchip Technology Inc. PIC16(L)F1526/27 Timer4, diagram of Reset TMRx TMRx Output Postscaler Comparator 1 PRx TxOUTPS<3:0> Preliminary ...
Page 180
... Timer2/4/6/8/10 Operation During Sleep The Timer2/4/6/8/10 timers cannot be operated while the processor is in Sleep mode. The contents of the TMR2/4/6/8/10 and PR2/4/6/8/10 registers will remain Section 19.2 unchanged while the processor is in Sleep mode. output signal Preliminary 2011 Microchip Technology Inc. ...
Page 181
... TMRxON: Timerx On bit 1 = Timer2/4 Timer2/4/6 is off bit 1-0 TxCKPS<1:0>: Timer2-type Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler Prescaler is 64 2011 Microchip Technology Inc. PIC16(L)F1526/27 R/W-0/0 R/W-0/0 R/W-0/0 TMRxON U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary ...
Page 182
... IOCIF 80 TMR2IE TMR1IE 81 TMR8IE CCP2IE 82 TMR4IE TMR3IE 83 TMR2IF TMR1IF 85 TMR8IF CCP2IF 86 TMR4IF TMR3IF 87 213* 213* 213* 213* 213* T2CKPS1 T2CKPS0 215 T4CKPS1 T4CKPS0 215 T6CKPS1 T6CKPS0 215 T8CKPS1 T8CKPS0 215 215 213* 213* 213* 213* 213* 2011 Microchip Technology Inc. ...
Page 183
... CCPx module. Register names, signals, I/O pins, and bit names may use the generic designator 'x' to indicate the use of a numeral to distinguish a particular module, when required. 2011 Microchip Technology Inc. PIC16(L)F1526/27 the same generic module Preliminary DS41458B-page 183 ...
Page 184
... CCPxIF interrupt flag bit of the PIRx register following any change in Operating mode. CCPRxL TMRxL Preliminary information on configuring TMR1 TMR3 TMR5 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● 2011 Microchip Technology Inc. ...
Page 185
... Sleep. When the device wakes from Sleep, Timer1/3/5 will continue from its previous state. Capture mode will operate during Sleep when Timer1/3/5 is clocked by an external clock source. 2011 Microchip Technology Inc. PIC16(L)F1526/27 20.1.6 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON ...
Page 186
... INTF IOCIF 80 TMR2IE TMR1IE 81 TMR8IE CCP2IE 82 TMR4IE TMR3IE 83 BCL2IE SSP2IE 84 TMR2IF TMR1IF 85 TMR8IF CCP2IF 86 TMR4IF TMR3IF 87 BCL2IF SSP2IF 88 — TMR1ON 176 — TMR3ON 176 — TMR5ON 176 T1GSS<1:0> 177 T3GSS<1:0> 177 2011 Microchip Technology Inc. ...
Page 187
... Holding Register for the Most Significant Byte of the 16-bit TMR6 Register TRISA TRISA7 TRISA6 TRISA5 — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode. Legend: * Page provides register information. 2011 Microchip Technology Inc. PIC16(L)F1526/27 Bit 5 Bit 4 Bit 3 Bit 2 T5GSPM T5GGO/DONE T5GVAL ...
Page 188
... CCPx COMPARE TIMER1/3/5 RESOURCES TMR1 TMR3 TMR5 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● more information on configuring ) should not be used in Compare OSC /4) or from an OSC 2011 Microchip Technology Inc. ...
Page 189
... CCPRxL register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1/3/5 Reset, will preclude the Reset from occurring. 2011 Microchip Technology Inc. PIC16(L)F1526/27 20.2.5 COMPARE DURING SLEEP The Compare mode is dependent upon the system clock (F ) for proper operation ...
Page 190
... INTF IOCIF 80 TMR2IE TMR1IE 81 TMR8IE CCP2IE 82 TMR4IE TMR3IE 83 BCL2IE SSP2IE 84 TMR2IF TMR1IF 85 TMR8IF CCP2IF 86 TMR4IF TMR3IF 87 BCL2IF SSP2IF 88 — TMR1ON 176 — TMR3ON 176 — TMR5ON 176 T1GSS<1:0> 177 T3GSS<1:0> 177 2011 Microchip Technology Inc. ...
Page 191
... Holding Register for the Most Significant Byte of the 16-bit TMR6 Register TRISA TRISA7 TRISA6 TRISA5 — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode. Legend: * Page provides register information. 2011 Microchip Technology Inc. PIC16(L)F1526/27 Bit 5 Bit 4 Bit 3 Bit 2 T5GSPM T5GGO/DONE T5GVAL ...
Page 192
... CCP3 ● ● CCP4 ● ● CCP5 ● CCP6 ● CCP7 ● CCP8 ● CCP9 ● CCP10 ● Preliminary 2011 Microchip Technology Inc. TMRx = PRx CCPxCON<5:4> CCPx TRIS ), or OSC TMR6 TMR8 TMR10 ● ● ● ● ● ● ● ● ...
Page 193
... Configuring the CxTSEL<1:0> bits in the CCPTMRSx register selects which Timer2/4/6/8/10 timer is used. See Table 20-6 for CCPx PWM Timer2/4/6/8/10 resources. 2011 Microchip Technology Inc. PIC16(L)F1526/27 20.3.4 PWM PERIOD The PWM period is specified by the PRx register of Timer2/4/6/8/10. The PWM period can be calculated ...
Page 194
... OSC Equation 20-4. PWM RESOLUTION log 4 PRx + 1 = ----------------------------------------- - bits 2 log = 20 MHz) OSC 156.3 kHz 208.3 kHz 0x3F 0x1F 0x17 MHz) OSC 153.85 kHz 200.0 kHz 0x19 0x0C 0x09 2011 Microchip Technology Inc. ...
Page 195
... T6CON — Legend: — = Unimplemented location, read as ‘ 0 ’. Shaded cells are not used by the PWM. * Page provides register information. 2011 Microchip Technology Inc. PIC16(L)F1526/27 20.3.9 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. ...
Page 196
... Page provides register information. DS41458B-page 196 Bit 5 Bit 4 Bit 3 Bit 2 T8OUTPS<3:0> TMR8ON T10OUTPS<3:0> TMR10ON TRISA5 TRISA4 TRISA3 TRISA2 Preliminary Register Bit 1 Bit 0 on Page T8CKPS<:0>1 176 T10CKPS<:0>1 176 179* 179* 179* 179* 179* TRISA1 TRISA0 120 2011 Microchip Technology Inc. ...
Page 197
... Compare mode: generate software interrupt only 1011 = Compare mode: Special Event Trigger (sets CCP10IF bit (CCP10), starts A/D conversion if A/D module (1) is enabled) 11xx = PWM mode 2011 Microchip Technology Inc. PIC16(L)F1526/27 R/W-0/0 R/W-0/0 R/W-0/0 DCxB<1:0> Unimplemented bit, read as ‘0’ ...
Page 198
... CCP1 is based off Timer4 in PWM mode 10 = CCP1 is based off Timer6 in PWM mode 11 = Reserved DS41458B-page 198 R/W-0/0 R/W-0/0 R/W-0/0 C2TSEL<1:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 C1TSEL<1:0> bit 0 2011 Microchip Technology Inc. ...
Page 199
... CCP5 is based off Timer5 in Capture/Compare mode When in PWM mode CCP5 is based off Timer2 in PWM mode 01 = CCP5 is based off Timer6 in PWM mode 10 = CCP5 is based off Timer8 in PWM mode 11 = Reserved 2011 Microchip Technology Inc. PIC16(L)F1526/27 R/W-0/0 R/W-0/0 R/W-0/0 C6TSEL<1:0> Unimplemented bit, read as ‘0’ ...
Page 200
... CCP9 is based off Timer8 in PWM mode 10 = CCP9 is based off Timer10 in PWM mode 11 = Reserved DS41458B-page 200 U-0 R/W-0/0 R/W-0/0 — C10TSEL<1:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary 2011 Microchip Technology Inc. R/W-0/0 R/W-0/0 C9TSEL<1:0> bit 0 ...