PIC16F1526T-I/PT Microchip Technology, PIC16F1526T-I/PT Datasheet - Page 188

• Manufacturer Part Number: PIC16F1526T-I/PT
• Description: 64-pin, 14KB Flash, 768B RAM, 10-bit ADC, 10xCCP, 2xSPI, 2xMI2C, 2xEUSART, 2.3V-
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1526T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16(L)F1526/27
20.2
The Compare mode function described in this section
is available and identical for CCP modules.
Compare mode makes use of the 16-bit Timer1/3/5
resource. The 16-bit value of the CCPRxH:CCPRxL
register pair is constantly compared against the 16-bit
value of the TMRxH:TMRxL register pair. When a
match occurs, one of the following events can occur:
• Toggle the CCPx output
• Set the CCPx output
• Clear the CCPx output
• Generate a Special Event Trigger
• Generate a Software Interrupt
The action on the pin is based on the value of the
CCPxM<3:0> control bits of the CCPxCON register. At
the same time, the interrupt flag CCPxIF bit is set.
All Compare modes can generate an interrupt.
Figure 20-2
Compare operation.
FIGURE 20-2:
DS41458B-page 188
CCPx
Pin
Output Enable
TRIS
Compare Mode
shows a simplified diagram of the
Q
Special Event Trigger
CCPxM<3:0>
R
S
Mode Select
Output
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Logic
Set CCPxIF Interrupt Flag
4
(PIRx)
Match
CCPRxH CCPRxL
TMRxH
Comparator
TMRxL
Preliminary
20.2.1
The user must configure the CCPx pin as an output by
clearing the associated TRIS bit.
Also, the CCPx pin function can be moved to
alternative pins using the APFCON register. Refer to
Section 12.1 “Alternate Pin Function”
details.
20.2.2
In Compare mode, Timer1/3/5 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
TABLE 20-3:
See
Control”
Timer1/3/5.
Note:
Note:
CCP10
Section 18.0 “Timer1/3/5 Module with Gate
CCP1
CCP2
CCP3
CCP4
CCP5
CCP6
CCP7
CCP8
CCP9
CCP
for
CCP PIN CONFIGURATION
Clearing the CCPxCON register will force
the CCPx compare output latch to the
default low level. This is not the PORT I/O
data latch.
TIMER1/3/5 MODE RESOURCE
Clocking Timer1/3/5 from the system clock
(F
mode. In order for Compare mode to
recognize the trigger event on the CCPx
pin, Timer1/3/5 must be clocked from the
instruction clock (F
external clock source.
OSC
more
) should not be used in Compare
CCPx COMPARE TIMER1/3/5
RESOURCES
TMR1
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 2011 Microchip Technology Inc.
information
OSC
TMR3
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/4) or from an
on
configuring
for more
TMR5
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