PIC16F1526T-I/PT Microchip Technology, PIC16F1526T-I/PT Datasheet - Page 82

• Manufacturer Part Number: PIC16F1526T-I/PT
• Description: 64-pin, 14KB Flash, 768B RAM, 10-bit ADC, 10xCCP, 2xSPI, 2xMI2C, 2xEUSART, 2.3V-
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1526T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16(L)F1526/27
7.6.3
The PIE2 register contains the interrupt enable bits, as
shown in
REGISTER 7-3:
DS41458B-page 82
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0/0
OSFIE
Register
PIE2 REGISTER
OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables the Oscillator Fail interrupt
0 = Disables the Oscillator Fail interrupt
TMR5GIE: Timer5 Gate Interrupt Enable bit
1 = Enables the Timer5 Gate Acquisition interrupt
0 = Disables the Timer5 Gate Acquisition interrupt
TMR3GIE: Timer3 Gate Interrupt Enable bit
1 = Enables the Timer3 Gate Acquisition interrupt
0 = Disables the Timer3 Gate Acquisition interrupt
Unimplemented: Read as ‘0’
BCL1IE: MSSP1 Bus Collision Interrupt Enable bit
1 = Enables the MSSP1 Bus Collision Interrupt
0 = Disables the MSSP1 Bus Collision Interrupt
TMR10IE: TMR10 to PR10 Match Interrupt Enable bit
1 = Enables the Timer10 to PR10 match interrupt
0 = Disables the Timer10 to PR10 match interrupt
TMR8IE: TMR8 to PR8 Match Interrupt Enable bit
1 = Enables the Timer8 to PR8 match interrupt
0 = Disables the Timer8 to PR8 match interrupt
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
TMR5GIE
7-3.
R/W-0/0
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
TMR3GIE
R/W-0/0
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
BCL1IE
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
TMR10IE
R/W-0/0
 2011 Microchip Technology Inc.
R/W-0/0
TMR8IE
R/W-0/0
CCP2IE
bit 0