PIC16F1526T-I/PT Microchip Technology, PIC16F1526T-I/PT Datasheet - Page 272

• Manufacturer Part Number: PIC16F1526T-I/PT
• Description: 64-pin, 14KB Flash, 768B RAM, 10-bit ADC, 10xCCP, 2xSPI, 2xMI2C, 2xEUSART, 2.3V-
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1526T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16(L)F1526/27
22.4.1
The EUSART module supports automatic detection
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RXx signal, the RXx signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Setting the ABDEN bit of the BAUDxCON register
starts
(Figure
the EUSART state machine is held in Idle. On the first
rising edge of the receive line, after the Start bit, the
SPxBRGL begins counting up using the BRG counter
clock as shown in
occur on the RXx/DTx pin at the end of the eighth bit
period. At that time, an accumulated value totaling the
proper BRG period is left in the SPxBRGH:SPxBRGL
register pair, the ABDEN bit is automatically cleared,
and the RCxIF interrupt flag is set. A read operation on
the RCxREG needs to be performed to clear the RCxIF
interrupt. RCxREG content should be discarded. When
calibrating for modes that do not use the SPxBRGH
register the user can verify that the SPxBRGL register
did not overflow by checking for 00h in the SPxBRGH
register.
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in
both the SPxBRGH and SPxBRGL registers are used
as a 16-bit counter, independent of the BRG16 bit set-
ting. While calibrating the baud rate period, the
SPxBRGH and SPxBRGL registers are clocked at
FIGURE 22-6:
DS41458B-page 272
RXx/DTx pin
BRG Value
BRG Clock
ABDEN bit
SPxBRGH
SPxBRGL
RCxIF bit
(Interrupt)
RCxREG
RCIDL
22.4.2). While the ABD sequence takes place,
Note 1:
Read
the
AUTO-BAUD DETECT
Set by User
The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
auto-baud
XXXXh
Table
AUTOMATIC BAUD RATE CALIBRATION
22-6. The fifth rising edge will
Table
calibration
0000h
22-6. During ABD,
Start
sequence
bit 0
XXh
XXh
Edge #1
Preliminary
bit 1
bit 2
Edge #2
1/8th the BRG base clock rate. The resulting byte mea-
surement is the average bit time when clocked at full
speed.
TABLE 22-6:
BRG16
Note:
Note 1: If the WUE bit is set with the ABDEN bit,
bit 3
0
0
1
1
2: It is up to the user to determine that the
3: During the auto-baud process, the
bit 4
Edge #3
BRGH
During the ABD sequence, SPxBRGL and
SPxBRGH registers are both used as a
16-bit counter, independent of BRG16
setting.
auto-baud detection will occur on the byte
following the Break character (see
Section 22.4.3
Break”
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
auto-baud counter starts counting at 1.
Upon
sequence, to achieve maximum accu-
racy,
SPxBRGH:SPxBRGL register pair.
0
1
0
1
bit 5
BRG COUNTER CLOCK
RATES
).
completion of the
subtract
BRG Base
bit 6
Edge #4
 2011 Microchip Technology Inc.
F
F
F
F
Clock
OSC
OSC
OSC
OSC
bit 7
/64
/16
/16
/4
“Auto-Wake-up
1
Stop bit
Edge #5
Auto Cleared
BRG ABD
001Ch
F
F
F
from
F
1Ch
00h
OSC
OSC
OSC
Clock
OSC
auto-baud
/512
/128
/128
/32
the
on