PIC16F1526T-I/PT Microchip Technology, PIC16F1526T-I/PT Datasheet - Page 105

• Manufacturer Part Number: PIC16F1526T-I/PT
• Description: 64-pin, 14KB Flash, 768B RAM, 10-bit ADC, 10xCCP, 2xSPI, 2xMI2C, 2xEUSART, 2.3V-
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1526T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.2.3
While executing code, program memory can only be
erased by rows. To erase a row:
1.
2.
3.
4.
5.
See
After the “BSF PMCON1,WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOP instructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms erase time. This is not Sleep mode as the
clocks and peripherals will continue to run. After the
erase cycle, the processor will resume operation with
the third instruction after the PMCON1 WRITE instruc-
tion.
 2011 Microchip Technology Inc.
Load the PMADRH:PMADRL register pair with
any address within the row to be erased.
Clear the CFGS bit of the PMCON1 register.
Set the FREE and WREN bits of the PMCON1
register.
Write 55h, then AAh, to PMCON2 (Flash
programming unlock sequence).
Set control bit WR of the PMCON1 register to
begin the erase operation.
Example
ERASING FLASH PROGRAM
MEMORY
11-2.
Preliminary
FIGURE 11-4:
PIC16(L)F1526/27
Program or Configuration Memory
Disable Write/Erase Operation
Enable Write/Erase Operation
Erase operation completes
Select Erase Operation
(PMADRH:PMADRL)
Re-enable Interrupts
Select Row Address
Disable Interrupts
Unlock Sequence
Erase Operation
CPU stalls while
Erase Operation
(FIGURE x-x)
(2ms typical)
(WREN = 1)
(WREN = 0)
FLASH PROGRAM
MEMORY ERASE
FLOWCHART
(FREE = 1)
Figure 11-3
(GIE = 0)
(GIE = 1)
(CFGS)
Select
Start
End
DS41458B-page 105