PIC16F1526T-I/PT Microchip Technology, PIC16F1526T-I/PT Datasheet - Page 283

• Manufacturer Part Number: PIC16F1526T-I/PT
• Description: 64-pin, 14KB Flash, 768B RAM, 10-bit ADC, 10xCCP, 2xSPI, 2xMI2C, 2xEUSART, 2.3V-
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1526T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.5.2.3
The operation of the Synchronous Master and Slave
modes is identical (
Master Reception”
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCxREG register. If the RCxIE enable bit is set,
the interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
TABLE 22-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
 2011 Microchip Technology Inc.
BAUD1CON
BAUD2CON
INTCON
PIE1
PIE4
PIR1
PIR4
RC1REG
RC1STA
RC2REG
RC2STA
SP1BRGL
SP1BRGH
SP2BRGL
SP2BRGH
TX1STA
TX2STA
Legend:
never Idle
Name
*
Page provides register information.
— = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave reception.
EUSART Synchronous Slave
Reception
TMR1GIE
TMR1GIF
ABDOVF
ABDOVF
CCP10IE
CCP10IF
CSRC
CSRC
SPEN
SPEN
Bit 7
GIE
), with the following exceptions:
Section 22.5.1.6 “Synchronous
CCP9IE
CCP9IF
RCIDL
RCIDL
PEIE
ADIE
ADIF
Bit 6
RX9
RX9
TX9
TX9
EUSART1 Baud Rate Generator, High Byte
EUSART2 Baud Rate Generator, High Byte
TMR0IE
EUSART1 Baud Rate Generator, Low Byte
EUSART2 Baud Rate Generator, Low Byte
RC1IE
RC2IE
RC1IF
RC2IF
SREN
SREN
TXEN
TXEN
Bit 5
—
—
EUSART1 Receive Register
EUSART2 Receive Register
Preliminary
SCKP
SCKP
TX1IE
TX2IE
TX1IF
TX2IF
CREN
CREN
SYNC
SYNC
INTE
Bit 4
CCP8IE
SSP1IE
SSP1IF
CCP8IF
ADDEN
ADDEN
SENDB
SENDB
BRG16
BRG16
22.5.2.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
IOCIE
Bit 3
Set the SYNC and SPEN bits and clear the
CSRC bit.
Set the RXx/DTx and TXx/CKx TRIS controls to
‘1’.
If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
RCxIE bit.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCxIF bit will be set when reception is
complete. An interrupt will be generated if the
RCxIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCxSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCxREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCxSTA
register or by clearing the SPEN bit which resets
the EUSART.
PIC16(L)F1526/27
TMR0IF
CCP1IE
CCP7IE
CCP1IF
CCP7IF
BRGH
BRGH
FERR
FERR
Bit 2
Synchronous Slave Reception
Set-up:
—
—
TMR2IE
TMR2IF
BCL2IE
BCL2IF
OERR
OERR
TRMT
TRMT
WUE
WUE
INTF
Bit 1
TMR1IE
TMR1IF
ABDEN
ABDEN
SSP2IE
SSP2IF
IOCIF
RX9D
RX9D
TX9D
TX9D
DS41458B-page 283
Bit 0
Register
on Page
260*
260*
267*
267*
267*
267*
264
264
266
266
265
265
94
97
98
97
93