PIC16F1526T-I/PT Microchip Technology, PIC16F1526T-I/PT Datasheet - Page 211

• Manufacturer Part Number: PIC16F1526T-I/PT
• Description: 64-pin, 14KB Flash, 768B RAM, 10-bit ADC, 10xCCP, 2xSPI, 2xMI2C, 2xEUSART, 2.3V-
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1526T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.2.6
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSPx clock is much faster than the system clock.
In Slave mode, when MSSPx interrupts are enabled,
after the master completes sending data, an MSSPx
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSPx inter-
rupts should be disabled.
TABLE 21-1:
 2011 Microchip Technology Inc.
ANSELF
INTCON
PIE1
PIE4
PIR1
PIR4
SSP1BUF
SSP2BUF
SSP1CON1
SSP2CON1
SSP1CON3
SSP2CON3
SSP1STAT
SSP2STAT
TRISC
TRISD
TRISF
Legend:
Name
*
SPI OPERATION IN SLEEP MODE
— = Unimplemented location, read as ‘ 0 ’. Shaded cells are not used by the MSSPx in SPI mode.
Page provides register information.
MSSPx Receive Buffer/Transmit Register
MSSPx Receive Buffer/Transmit Register
TMR1GIE
TMR1GIF
CCP10IE
CCP10IF
ACKTIM
ACKTIM
TRISC7
TRISD7
TRISF7
ANSF7
WCOL
WCOL
Bit 7
SMP
SMP
GIE
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
CCP9IE
CCP9IF
TRISC6
TRISD6
SSPOV
SSPOV
TRISF6
ANSF6
ADIE
PCIE
PCIE
Bit 6
PEIE
ADIF
CKE
CKE
TMR0IE
TRISC5
TRISD5
SSPEN
SSPEN
TRISF5
ANSF5
RC1IE
RC2IE
RC1IF
RC2IF
SCIE
SCIE
Bit 5
D/A
D/A
TRISC4
TRISD4
TRISF4
ANSF4
BOEN
BOEN
TX1IE
TX2IE
TX1IF
TX2IF
Preliminary
INTE
Bit 4
CKP
CKP
P
P
CCP8IE
SSP1IE
SSP1IF
CCP8IF
TRISC3
TRISD3
TRISF3
SDAHT
SDAHT
ANSF3
IOCIE
Bit 3
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the
MSSPx interrupt flag bit will be set and if enabled, will
wake the device.
S
S
PIC16(L)F1526/27
TMR0IF
CCP1IE
CCP7IE
CCP1IF
CCP7IF
TRISC2
TRISD2
SBCDE
SBCDE
TRISF2
ANSF2
Bit 2
R/W
R/W
SSPM<3:0>
SSPM<3:0>
TMR2IE
TMR2IF
TRISC1
TRISD1
BCL2IE
BCL2IF
TRISF1
ANSF1
AHEN
AHEN
Bit 1
INTF
UA
UA
TMR1IE
TMR1IF
TRISC0
TRISD0
SSP2IE
SSP2IF
TRISF0
ANSF0
DHEN
DHEN
IOCIF
Bit 0
DS41458B-page 211
BF
BF
Register
on Page
205*
205*
136
251
251
253
253
249
249
126
129
135
80
81
84
85
88