PIC16F1526T-I/PT Microchip Technology, PIC16F1526T-I/PT Datasheet - Page 296

• Manufacturer Part Number: PIC16F1526T-I/PT
• Description: 64-pin, 14KB Flash, 768B RAM, 10-bit ADC, 10xCCP, 2xSPI, 2xMI2C, 2xEUSART, 2.3V-
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1526T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16(L)F1526/27
DECFSZ
Syntax:
Operands:
Operation:
Status Affected:
Description:
GOTO
Syntax:
Operands:
Operation:
Status Affected:
Description:
INCF
Syntax:
Operands:
Operation:
Status Affected:
Description:
DS41458B-page 296
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0  f  127
d  [ 0 , 1 ]
(f) - 1  (destination);
skip if result = 0
None
The contents of register ‘f’ are decre-
mented. If ‘d’ is ‘ 0 ’, the result is placed
in the W register. If ‘d’ is ‘ 1 ’, the result
is placed back in register ‘f’.
If the result is ‘ 1 ’, the next instruction is
executed. If the result is ‘ 0 ’, then a
NOP is executed instead, making it a
2-cycle instruction.
Unconditional Branch
[ label ]
0  k  2047
k  PC<10:0>
PCLATH<6:3>  PC<14:11>
None
GOTO is an unconditional branch. The
eleven-bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTO is a two-cycle instruction.
Increment f
[ label ]
0  f  127
d  [ 0 , 1 ]
(f) + 1  (destination)
Z
The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘ 0 ’, the result is placed
in the W register. If ‘d’ is ‘ 1 ’, the result
is placed back in register ‘f’.
GOTO k
INCF f,d
Preliminary
INCFSZ
Syntax:
Operands:
Operation:
Status Affected:
Description:
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Increment f, Skip if 0
[ label ]
0  f  127
d  [ 0 , 1 ]
(f) + 1  (destination),
None
The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘ 0 ’, the result is placed
in the W register. If ‘d’ is ‘ 1 ’, the result
is placed back in register ‘f’.
If the result is ‘ 1 ’, the next instruction is
executed. If the result is ‘ 0 ’, a NOP is
executed instead, making it a 2-cycle
instruction.
Inclusive OR W with f
[ label ]
0  f  127
d  [ 0 , 1 ]
(W) .OR. (f)  (destination)
Z
Inclusive OR the W register with regis-
ter ‘f’. If ‘d’ is ‘ 0 ’, the result is placed in
the W register. If ‘d’ is ‘ 1 ’, the result is
placed back in register ‘f’.
skip if result = 0
Inclusive OR literal with W
[ label ]
0  k  255
(W) .OR. k  (W)
Z
The contents of the W register are
OR’ed with the eight-bit literal ‘k’. The
result is placed in the W register.
 2011 Microchip Technology Inc.
INCFSZ f,d
IORWF
IORLW k
f,d