PIC16F1526T-I/PT Microchip Technology, PIC16F1526T-I/PT Datasheet - Page 27

• Manufacturer Part Number: PIC16F1526T-I/PT
• Description: 64-pin, 14KB Flash, 768B RAM, 10-bit ADC, 10xCCP, 2xSPI, 2xMI2C, 2xEUSART, 2.3V-
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1526T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 3-3:
Legend:
Note
C0Ch
80Bh
80Ch
C00h
C0Bh
C6Fh
C70h
C7Fh
800h
81Fh
820h
86Fh
870h
87Fh
1:
Unimplemented
Unimplemented
Core Registers
Common RAM
Core Registers
Common RAM
Read as ‘0’
Read as ‘0’
BANK 16
(Table
80 Bytes
70h – 7Fh)
BANK 24
(Table
70h – 7Fh)
(Accesses
(Accesses
General
Purpose
Register
PIC16(L)F1527 only.
3-2)
3-2)
= Unimplemented data memory locations, read as ‘0’.
(1)
PIC16(L)F1526/27 MEMORY MAP (CONTINUED)
C8Ch
CEFh
88Bh
88Ch
8A0h
8EFh
8FFh
C80h
C8Bh
CF0h
CFFh
880h
89Fh
8F0h
Unimplemented
Unimplemented
Core Registers
Core Registers
Common RAM
Common RAM
BANK 17
Read as ‘0’
BANK 25
Read as ‘0’
(Table
80 Bytes
70h – 7Fh)
(Table
70h – 7Fh)
(Accesses
(Accesses
General
Purpose
Register
3-2)
3-2)
(1)
D0Bh
D0Ch
90Bh
90Ch
97Fh
D00h
D6Fh
D70h
D7Fh
900h
91Fh
920h
96Fh
970h
Unimplemented
Unimplemented
Core Registers
Core Registers
Common RAM
Common RAM
BANK 18
Read as ‘0’
80 Bytes
70h – 7Fh)
BANK 26
Read as ‘0’
70h – 7Fh)
(Table
(Table
(Accesses
(Accesses
General
Purpose
Register
3-2)
3-2)
(1)
D8Bh
D8Ch
DEFh
DFFh
98Bh
98Ch
9EFh
9F0h
9FFh
D80h
DF0h
980h
Unimplemented
Unimplemented
Core Registers
Core Registers
Common RAM
Common RAM
Read as ‘0’
Read as ‘0’
BANK 19
70h – 7Fh)
BANK 27
70h – 7Fh)
(Table
(Accesses
(Table
(Accesses
3-2)
3-2)
A0Ch
E0Ch
A00h
A0Bh
A6Fh
A70h
A7Fh
E00h
E0Bh
E6Fh
E70h
E7Fh
Unimplemented
Unimplemented
Core Registers
Core Registers
Common RAM
Common RAM
Read as ‘0’
Read as ‘0’
BANK 20
70h – 7Fh)
BANK 28
70h – 7Fh)
(Table
(Accesses
(Table
(Accesses
3-2)
3-2)
A8Bh
A8Ch
AEFh
AFFh
E8Bh
E8Ch
EEFh
EFFh
A80h
AF0h
E80h
EF0h
Unimplemented
Unimplemented
Core Registers
Core Registers
Common RAM
Common RAM
Read as ‘0’
Read as ‘0’
BANK 21
(Table
70h – 7Fh)
BANK 29
(Table
70h – 7Fh)
(Accesses
(Accesses
3-2)
3-2)
B0Bh
B0Ch
F0Ch
B00h
B6Fh
B70h
B7Fh
F00h
F0Bh
F6Fh
F70h
F7Fh
Unimplemented
Unimplemented
Core Registers
Common RAM
Core Registers
Common RAM
Read as ‘0’
Read as ‘0’
BANK 22
(Table
70h – 7Fh)
BANK 30
(Table
70h – 7Fh)
(Accesses
(Accesses
3-2)
3-2)
B8Bh
B8Ch
BEFh
BFFh
B80h
BF0h
Unimplemented
Core Registers
Common RAM
Read as ‘0’
BANK 23
(Table
70h – 7Fh)
(Accesses
3-2)