PIC16F1526T-I/PT Microchip Technology, PIC16F1526T-I/PT Datasheet - Page 94

• Manufacturer Part Number: PIC16F1526T-I/PT
• Description: 64-pin, 14KB Flash, 768B RAM, 10-bit ADC, 10xCCP, 2xSPI, 2xMI2C, 2xEUSART, 2.3V-
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1526T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16(L)F1526/27
8.3
REGISTER 8-1:
TABLE 8-1:
DS41458B-page 94
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-2
bit 1
bit 0
Note 1:
INTCON
IOCBF
IOCBN
IOCBP
PIE1
PIE2
PIE3
PIE4
PIR1
PIR2
PIR3
PIR4
STATUS
VREGCON
WDTCON
Legend:
Note 1:
Name
U-0
—
2:
Power Control Registers
(1)
PIC16F1526/27 only.
See Section
— = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode.
PIC16F1526/27 only.
TMR1GIE
TMR1GIF
CCP10IE
CCP10IF
IOCBN7
IOCBF7
IOCBP7
CCP6IE
CCP6IF
Unimplemented: Read as ‘0’
VREGPM: Voltage Regulator Power Mode Selection bit
1 = Low-Power Sleep mode enabled in Sleep
0 = Normal Power mode enabled in Sleep
Reserved: Read as ‘1’. Maintain this bit set.
OSFIE
OSFIF
Bit 7
GIE
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
—
—
—
Draws lowest current in Sleep, slower wake-up
Draws higher current in Sleep, faster wake-up
U-0
—
VREGCON: VOLTAGE REGULATOR CONTROL REGISTER
25.0 “Electrical
TMR5GIE
TMR5GIF
IOCBN6
IOCBF6
IOCBP6
CCP5IE
CCP9IE
CCP5IF
CCP9IF
PEIE
ADIE
ADIF
Bit 6
—
—
—
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U-0
—
TMR3GIE
TMR3GIF
TMR0IE
IOCBN5
IOCBP5
IOCBF5
CCP4IE
CCP4IF
RC1IE
RC2IE
RC1IF
RC2IF
Bit 5
Specifications”.
—
—
IOCBN4
IOCBF4
IOCBP4
CCP3IE
CCP3IF
U-0
Preliminary
TX1IE
TX2IE
—
TX1IF
TX2IF
Bit 4
INTE
TO
—
—
—
WDTPS<4:0>
(2)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
IOCBN3
IOCBF3
IOCBP3
TMR6IE
CCP8IE
TMR6IF
CCP8IF
SSP1IE
SSP1IF
BCL1IF
BCLIE
IOCIE
(2)
Bit 3
PD
—
U-0
—
TMR10IE
TMR10IF
TMR0IF
IOCBN2
IOCBP2
TMR5IE
TMR5IF
IOCBF2
CCP1IE
CCP7IE
CCP1IF
CCP7IF
Bit 2
—
Z
U-0
—
VREGPM
IOCBN1
IOCBP1
TMR2IE
TMR8IE
TMR4IE
IOCBF1
TMR2IF
TMR8IF
TMR4IF
BCL2IE
BCL2IF
Bit 1
INTF
DC
 2011 Microchip Technology Inc.
VREGPM
R/W-0/0
(1)
SWDTEN
Reserved
IOCBN0
IOCBF0
IOCBP0
TMR1IE
CCP2IE
TMR3IE
TMR1IF
TMR3IF
SSP2IE
CCP2IF
SSP2IF
IOCIF
Bit 0
C
Reserved
Register on
R/W-1/1
Page
143
143
143
80
81
82
83
84
85
86
87
88
23
94
99
bit 0