LTC2494IUHF#PBF Linear Technology, LTC2494IUHF#PBF Datasheet - Page 17

• Manufacturer Part Number: LTC2494IUHF#PBF
• Description: IC ADC 16BIT W/PGA 38-QFN
• Manufacturer: Linear Technology

Specifications of LTC2494IUHF#PBF

• Number Of Bits: 16
• Sampling Rate (per Second): 15
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 480µW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 38-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

applications inForMation
Bit 20 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 21 also pro-
vides underrange and overrange indication. If both Bit 21
and Bit 20 are HIGH, the differential input voltage is above
+FS. If both Bit 21 and Bit 20 are LOW, the differential
input voltage is below –FS. The function of these bits is
summarized in Table 1.
Table 1. LTC2494 Status Bits
Input Range
V
0V ≤ V
–0.5 • V
V
Bits 20 to 4 are the 16-bit plus sign conversion result
MSB first.
Bit 4 is the least significant bit (LSB
Bits 3 to 0 are always LOW.
Data is shifted out of the SDO pin under control of the
serial clock (SCK) (see Figure 3). Whenever CS is HIGH,
SDO remains high impedance and SCK is ignored.
(EXTERNAL)
IN
IN
≥ 0.5 • V
< –0.5 • V
SDO
SCK
IN
SDI
CS
REF
< 0.5 • V
CONVERSION
/Gain ≤ V
REF
DON'T CARE
REF
Hi-Z
/Gain
/Gain
REF
IN
/Gain
< 0V
SLEEP
Figure 3. Channel Selection, Configuration Selection and Data Output Timing
Bit 23
EOC
BIT 23
1
EOC
0
0
0
0
1
BIT 22
“0”
0
2
Bit 22
DMY
0
0
0
0
16
BIT 21
SIG
EN
3
).
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11
MSB
SGL
Bit 21
4
SIG
1/0
1
0
0
ODD
5
Bit 20
MSB
A2
6
1
0
1
0
DATA INPUT/OUTPUT
A1
7
A0
In order to shift the conversion result out of the device,
CS must first be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes in real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
microcontroller. Bit 23 (EOC) can be captured on the first
rising edge of SCK. Bit 22 is shifted out of the device on
the first falling edge of SCK. The final data bit (Bit 0) is
shifted out on the on the falling edge of the 23rd SCK and
may be latched on the rising edge of the 24th SCK pulse.
On the falling edge of the 24th SCK pulse, SDO goes HIGH
indicating the initiation of a new conversion cycle. This
bit serves as EOC (Bit 23) for the next conversion cycle.
Table 2 summarizes the output data format.
As long as the voltage on the IN
between –0.3V and V
erating range) a conversion result is generated for any
differential input voltage V
to +FS = 0.5 • V
greater than +FS, the conversion result is clamped to the
value corresponding to +FS + 1LSB. For differential input
voltages below –FS, the conversion result is clamped to
the value –FS – 1LSB.
8
EN2
9
IM
10
FA
11
REF
FB
12
/Gain. For differential input voltages
CC
SPD
13
+ 0.3V (absolute maximum op-
IN
BIT 10
GS2
from –FS = –0.5 • V
14
BIT 9
GS1
15
+
and IN
GS0
16
LTC2494
–
BIT 0
pins remains
24
DON'T CARE
REF
CONVERSION

Hi-Z
/Gain
2494fd
2494 F03