LTC2494IUHF#PBF Linear Technology, LTC2494IUHF#PBF Datasheet - Page 23

• Manufacturer Part Number: LTC2494IUHF#PBF
• Description: IC ADC 16BIT W/PGA 38-QFN
• Manufacturer: Linear Technology

Specifications of LTC2494IUHF#PBF

• Number Of Bits: 16
• Sampling Rate (per Second): 15
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 480µW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 38-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

applications inForMation
(EXTERNAL)
edge). The channel selection and converter configuration
mode will be used for the following conversion cycle. If
the input channel or converter configuration is changed
during this I/O cycle, the new settings take effect on the
conversion cycle following the data input/output cycle.
The output data is shifted out the SDO pin on each falling
edge of SCK. This enables external circuitry to latch the
output on the rising edge of SCK. EOC can be latched on
the first rising edge of SCK and the last bit of the conver-
sion result can be latched on the 24th rising edge of SCK.
On the 24th falling edge of SCK, the device begins a new
conversion and SDO goes HIGH (EOC = 1) indicating a
conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Typically, CS remains LOW during the data output/input
state. However, the data output state may be aborted by
SDO
SCK
SDI
CS
CONVERSION
DON'T CARE
SLEEP
Hi-Z
BIT 23
1
EOC
1
BIT 22
“0”
Figure 6. External Serial Clock, Single Cycle Operation
10µF
0
2
2.7V TO 5.5V
BIT 21
SIG
EN
3
0.1V TO V
0.1µF
REFERENCE
ANALOG
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13
INPUTS
VOLTAGE
MSB
SGL
4
CC
ODD
5
•
•
•
•
•
•
28
29
30
15
16
23
8
7
V
REF
REF
CH0
CH7
CH8
CH15
COM
A2
CC
•
•
•
•
•
•
6
LTC2494
+
–
A1
7
SDO
GND
SCK
SDI
CS
f
DATA INPUT/OUTPUT
O
pulling CS HIGH any time between the 1st falling edge
and the 24th falling edge of SCK (see Figure 7). On the
rising edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge
of SCK, the new input channel is loaded and valid for the
next conversion cycle. If CS goes HIGH between the 8th
falling edge and the 16th falling edge of SCK, the new
channel is still loaded, but the converter configuration
remains unchanged. In order to program both the input
channel and converter configuration, CS must go HIGH
after the 16th falling edge of SCK (at this point all data
has been shifted into the device).
1,3,4,5,6,31,32,33,39
A0
34
38
35
37
36
8
EN2
9
4-WIRE
SPI INTERFACE
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
IM
10
FA
11
BIT 12 BIT 11
FB
12
SPD
13
BIT 10
GS2
14
GS1
BIT 9
15
GS0
16
LTC2494
DON'T CARE
BIT 0
24
CONVERSION

2494 F06
Hi-Z
2494fd