LTC2494IUHF#PBF Linear Technology, LTC2494IUHF#PBF Datasheet - Page 25

• Manufacturer Part Number: LTC2494IUHF#PBF
• Description: IC ADC 16BIT W/PGA 38-QFN
• Manufacturer: Linear Technology

Specifications of LTC2494IUHF#PBF

• Number Of Bits: 16
• Sampling Rate (per Second): 15
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 480µW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 38-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

applications inForMation
External Serial Clock, 3-Wire I/O
This timing mode uses a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal (see Figure 8).
CS is permanently tied to ground, simplifying the user
interface or isolation barrier.
The external serial clock mode is selected at the end of
the power-on reset (POR) cycle. The POR cycle is typically
concluded 4ms after V
SCK at this time determines if SCK is internally generated
or externally applied. In order to enter the external SCK
mode, SCK must be driven LOW prior to the end of the
POR cycle.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller. EOC = 1 while the conversion is in
progress and EOC = 0 once the conversion is complete.
On the falling edge of EOC, the conversion result is load-
(INTERNAL)
SDO
SCK
SDI
CS
CONVERSION
DON'T CARE
SLEEP
CC
<t
exceeds 2V. The level applied to
EOCTEST
BIT 23
1
EOC
1
BIT 22
“0”
Figure 9. Internal Serial Clock, Single Cycle Operation
0
2
10µF
2.7V TO 5.5V
BIT 21
SIG
EN
3
0.1V TO V
REFERENCE
0.1µF
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13
MSB
ANALOG
SGL
INPUTS
VOLTAGE
4
CC
ODD
5
•
•
•
•
•
•
28
29
30
15
16
23
8
7
A2
V
REF
REF
CH0
CH7
CH8
CH15
COM
6
CC
•
•
•
•
•
•
LTC2494
+
–
A1
7
GND
SDO
SCK
SDI
DATA INPUT/OUTPUT
CS
ing into an internal static shift register. The output data
can now be shifted out the SDO pin under control of the
externally applied SCK signal. Data is updated on the fall-
ing edge of SCK. The input data is shifted into the device
through the SDI pin on the rising edge of SCK. On the
24th falling edge of SCK, SDO goes HIGH, indicating a
new conversion has begun. This data now serves as EOC
for the next conversion.
Internal Serial Clock, Single Cycle Operation
This timing mode uses the internal serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 9).
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be floating or pulled HIGH
before the conclusion of the POR cycle and prior to each
falling edge of CS. An internal weak pull-up resistor is active
on the SCK pin during the falling edge of CS; therefore,
the internal SCK mode is automatically selected if SCK is
not externally driven.
f
O
A0
1,3,4,5,6,31,32,33,39
8
34
38
35
37
36
EN2
9
4-WIRE
SPI INTERFACE
IM
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
10
FA
11
V
BIT 12 BIT 11
CC
FB
12
OPTIONAL
10k
SPD
13
BIT 10
GS2
14
BIT 9
GS1
15
GS0
16
LTC2494
BIT 0
24
DON'T CARE
Hi-Z

CONVERSION
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