ADC0858CIN National Semiconductor, ADC0858CIN Datasheet - Page 24

• Manufacturer Part Number: ADC0858CIN
• Description: IC DATA ACQUISITION/MON 20-DIP
• Manufacturer: National Semiconductor
• Type: Data Acquisition System (DAS)r

Specifications of ADC0858CIN

• Resolution (bits): 8 b
• Data Interface: NSC MICROWIRE™, Serial
• Voltage Supply Source: Single Supply
• Voltage - Supply: 5V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Sampling Rate (per Second): -
• Other names: *ADC0858CIN

3 0 Watchdog Mode
their respective window limits A logical ‘‘1’’ will be placed in
the appropriate location of the status register for each limit
that is crossed as the device cycles through the remaining
channels Note that the tag register is updated only once
i e when the first limit is exceeded After the last limit com-
parison is made subsequent to the first limit crossing the
device will cease any further limit comparisons and will
cause the interrupt pin to go low Taking CS low causes the
data in the status and tag registers to be transmitted along
with the programmed channel configuration information In
addition an extra bit P is inserted between the channel
and status information This bit is updated to a logic ‘‘1’’ in
case of a power interruption
The format for the output data is as shown below
The order in which data is transmitted is as follows
(ADC0851 or ADC0858)
It is important to note that any channel that is disabled will
not cause an interrupt Furthermore when operated in the
differential mode the arithmetic difference of the two volt-
ages will be compared with the lower and upper limits for
the lower numbered channel For example with CH0 and
CH1 operating as a differential input pair the CH0 limits will
apply
Consider an example where the lower limit of CH1 is
crossed first and while the remaining limits are being
checked the upper limit of CH0 is crossed Figure 8 illus-
trates the sequence of events for the ADC0851 During
watchdog operation CH0’s lower limit stored in the RAM is
compared against the input voltage at CH0 Since no limit
crossing is detected the upper limit is compared against
CH0 input voltage Again no limit crossing is detected and
so CH1’s lower limit is next compared against the CH1 input
voltage This time a limit crossing is detected and a logic
‘‘1’’ is now stored in the MSB (S3) position of the status
register (see Table IV(a)) Also the Tag register is updated
with the corresponding address (0 0 1 0) from Table IV(a)
The device now cycles through the remaining channels
once more Since no limit crossing is detected for the upper
limit of CH1 a logic ‘‘0’’ is stored for S2 of the status regis-
ter Similarly a logic ‘‘0’’ is stored for S1 of the status regis-
ter Finally to complete the cycle the last limit (upper limit of
CH0) is checked and a limit crossing is detected Conse-
quently a logic ‘‘1’’ is stored for S0 Note that the Tag regis-
Tags (4 bits) MSB (T3) first
Channel configuration (12 bits) MSB (C11) first
Power interrupt (1 bit)
Status (4 bits for ADC0851 16 bits for ADC0858) MSB
(S3 S15) first
Data Output (DO) Word ADC0851
Data Output (DO) Word ADC0858
(Continued)
TL H 11021– 46
TL H 11021– 47
24
Figure 9 shows the procedure for normalizing the status in-
Figure 9 for the ADC0858 demonstrates how status bit nor-
ter is only updated once when the first limit crossing is de-
tected thus indicating which channel first exceeded its lower
or upper limit
(Example Lower limit of CH1 is crossed first During cycle through upper
limit of CH0 is crossed)
Assuming that there is no power interruption and that the
ADC0851 was configured for single ended operation the
output word for our example would be
(Example of ADC0851 Data Output Single ended input
Lower limit of CH1 fails first During cycle through upper
limit CH0 failure is detected)
X
The ADC0858 operates similar to the ADC0851 except that
the ADC0858 has a 16-bit status word for the sixteen limits
and sixteen tag addresses (See Table IV(b)) The output
word transmitted to the microprocessor not only contains
information as to how the channels are configured but also
which input crossed which limit If desired the microproces-
sor can go through a status bit normalization routine to nor-
malize the status information with the tag number as will be
discussed next
3 3 STATUS BIT NORMALIZATION
formation Let’s consider the example cited earlier for the
ADC0851 In our example the lower limit of CH1 was
crossed first and during cycle-through upper limit CH0
crossing was detected The serial status data is thus 1 0 0 1
and the tag data 0 0 1 0 corresponds to tag
IVa) Since the most significant bit (S3) of the status data is
transmitted first the data stored in the microprocessor’s
memory is 1 0 0 1 The microprocessor next computes the
tag number from the tag data and rotates the status bits left
‘‘TAG’’ places as in Figure 9 For our example the status
bits are rotated by shifting left 2 places The status informa-
tion in the microprocessor’s memory is now normalized i e
U0 corresponds to tag 0 U1 corresponds to tag 1 and so
on From the example in Figure 9 we can see that the status
register in the microprocessor’s memory shows that tag 2
and tag 1 failed The ADC0858 uses a 16-bit status word
and operates similar to the ADC0851 An example shown in
malization is carried out
T3 T2 T1 T0 C11 C10 C9 C8 C7
0 0 1 0
e
Don’t care whatever bit was initially programmed (ADC0851 only)
FIGURE 8 Example of Limit Crossing
X
Detection (ADC0851)
X
X X X
C1 C0 P S3 S2 S1 S0
0 0 0 1 0 0 1
2 (see Table
TL H 11021 – 45