IC CYCLONE II FPGA 5K 256-FBGA

 

EP2C5F256C8

Manufacturer Part NumberEP2C5F256C8
DescriptionIC CYCLONE II FPGA 5K 256-FBGA
ManufacturerAltera
SeriesCyclone® II
EP2C5F256C8 datasheets

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Specifications of EP2C5F256C8

Number Of Logic Elements/cells4608Number Of Labs/clbs288
Total Ram Bits119808Number Of I /o158
Voltage - Supply1.15 V ~ 1.25 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case256-FBGA
Family NameCyclone® IINumber Of Logic Blocks/elements4608
# I/os (max)158Frequency (max)402.58MHz
Process Technology90nmOperating Supply Voltage (typ)1.2V
Logic Cells4608Ram Bits119808
Operating Supply Voltage (min)1.15VOperating Supply Voltage (max)1.25V
Operating Temp Range0C to 85COperating Temperature ClassificationCommercial
MountingSurface MountPin Count256
Package TypeFBGANo. Of Macrocells4608
Family TypeCyclone IINo. Of I/o's158
Clock ManagementPLLI/o Supply Voltage3.6V
Operating Frequency Max320MHzRohs CompliantNo
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantNumber Of Gates-
Other names544-1446  
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Timing Specifications
Table 5–48. RSDS Transmitter Timing Specification (Part 2 of 2)
–6 Speed Grade
Symbol
Conditions
Min
TCCS
—
—
Output
—
—
jitter (peak
to peak)
t
20–80%,
—
R I S E
C
= 5 pF
L O A D
t
80–20%,
—
F A L L
C
= 5 pF
L O A D
t
—
—
L O C K
Note to
Table
5–48:
(1)
These specifications are for a three-resistor RSDS implementation. For single-resistor RSDS in ×10 through ×2
modes, the maximum data rate is 170 Mbps and the corresponding maximum input clock frequency is 85 MHz.
For single-resistor RSDS in ×1 mode, the maximum data rate is 170 Mbps, and the maximum input clock frequency
is 170 MHz. For more information about the different RSDS implementations, refer to the
Interfaces in Cyclone II Devices
chapter of the Cyclone II Device Handbook.
In order to determine the transmitter timing requirements, RSDS receiver
timing requirements on the other end of the link must be taken into
consideration. RSDS receiver timing parameters are typically defined as
t
and t
SU
specifications are t
for the timing budget.
The AC timing requirements for RSDS are shown in
5–58
Cyclone II Device Handbook, Volume 1
–7 Speed Grade
Typ
Max(1)
Min
Typ
Max(1)
—
200
—
—
200
—
500
—
—
500
500
—
—
500
—
500
—
—
500
—
100
—
100
requirements. Therefore, the transmitter timing parameter
H
(minimum) and t
CO
–8 Speed Grade
Unit
Min
Typ
Max(1)
—
—
200
ps
—
—
500
ps
—
500
—
ps
—
500
—
ps
μs
—
—
100
High-Speed Differential
(maximum). Refer to
Figure 5–4
CO
Figure
5–5.
Altera Corporation
February 2008

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