IC CYCLONE II FPGA 5K 256-FBGA

 

EP2C5F256C8

Manufacturer Part NumberEP2C5F256C8
DescriptionIC CYCLONE II FPGA 5K 256-FBGA
ManufacturerAltera
SeriesCyclone® II
EP2C5F256C8 datasheets

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Specifications of EP2C5F256C8

Number Of Logic Elements/cells4608Number Of Labs/clbs288
Total Ram Bits119808Number Of I /o158
Voltage - Supply1.15 V ~ 1.25 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case256-FBGA
Family NameCyclone® IINumber Of Logic Blocks/elements4608
# I/os (max)158Frequency (max)402.58MHz
Process Technology90nmOperating Supply Voltage (typ)1.2V
Logic Cells4608Ram Bits119808
Operating Supply Voltage (min)1.15VOperating Supply Voltage (max)1.25V
Operating Temp Range0C to 85COperating Temperature ClassificationCommercial
MountingSurface MountPin Count256
Package TypeFBGANo. Of Macrocells4608
Family TypeCyclone IINo. Of I/o's158
Clock ManagementPLLI/o Supply Voltage3.6V
Operating Frequency Max320MHzRohs CompliantNo
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantNumber Of Gates-
Other names544-1446  
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Page 69/168

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I/O Banks
The I/O pins on Cyclone II devices are grouped together into I/O banks
and each bank has a separate power bus. EP2C5 and EP2C8 devices have
four I/O banks (see
EP2C50, and EP2C70 devices have eight I/O banks (see
Each device I/O pin is associated with one I/O bank. To accommodate
voltage-referenced I/O standards, each Cyclone II I/O bank has a VREF
bus. Each bank in EP2C5, EP2C8, EP2C15, EP2C20, EP2C35, and EP2C50
devices supports two VREF pins and each bank of EP2C70 supports four
VREF pins. When using the VREF pins, each VREF pin must be properly
connected to the appropriate voltage level. In the event these pins are not
used as VREF pins, they may be used as regular I/O pins.
The top and bottom I/O banks (banks 2 and 4 in EP2C5 and EP2C8
devices and banks 3, 4, 7, and 8 in EP2C15, EP2C20, EP2C35, EP2C50, and
EP2C70 devices) support all I/O standards listed in
PCI/PCI-X I/O standards. The left and right side I/O banks (banks 1 and
3 in EP2C5 and EP2C8 devices and banks 1, 2, 5, and 6 in EP2C15, EP2C20,
EP2C35, EP2C50, and EP2C70 devices) support I/O standards listed in
Table
I/O standards. See
standards.
The top and bottom I/O banks (banks 2 and 4 in EP2C5 and EP2C8
devices and banks 3, 4, 7, and 8 in EP2C15, EP2C20, EP2C35, EP2C50, and
EP2C70 devices) support DDR2 memory up to 167 MHz/333 Mbps and
QDR memory up to 167 MHz/668 Mbps. The left and right side I/O
banks (1 and 3 of EP2C5 and EP2C8 devices and 1, 2, 5, and 6 of EP2C15,
EP2C20, EP2C35, EP2C50, and EP2C70 devices) only support SDR and
DDR SDRAM interfaces. All the I/O banks of the Cyclone II devices
support SDR memory up to 167 MHz/167 Mbps and DDR memory up to
167 MHz/333 Mbps.
1
Altera Corporation
February 2007
Figure
2–28), while EP2C15, EP2C20, EP2C35,
2–17, except SSTL-18 class II, HSTL-18 class II, and HSTL-15 class II
Table 2–17
for a complete list of supported I/O
DDR2 and QDRII interfaces may be implemented in Cyclone II
side banks if the use of class I I/O standard is acceptable.
Cyclone II Device Handbook, Volume 1
Cyclone II Architecture
Figure
2–29).
Table
2–17, except the
2–57

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