IC CYCLONE II FPGA 5K 256-FBGA

 

EP2C5F256C8

Manufacturer Part NumberEP2C5F256C8
DescriptionIC CYCLONE II FPGA 5K 256-FBGA
ManufacturerAltera
SeriesCyclone® II
EP2C5F256C8 datasheets

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Specifications of EP2C5F256C8

Number Of Logic Elements/cells4608Number Of Labs/clbs288
Total Ram Bits119808Number Of I /o158
Voltage - Supply1.15 V ~ 1.25 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case256-FBGA
Family NameCyclone® IINumber Of Logic Blocks/elements4608
# I/os (max)158Frequency (max)402.58MHz
Process Technology90nmOperating Supply Voltage (typ)1.2V
Logic Cells4608Ram Bits119808
Operating Supply Voltage (min)1.15VOperating Supply Voltage (max)1.25V
Operating Temp Range0C to 85COperating Temperature ClassificationCommercial
MountingSurface MountPin Count256
Package TypeFBGANo. Of Macrocells4608
Family TypeCyclone IINo. Of I/o's158
Clock ManagementPLLI/o Supply Voltage3.6V
Operating Frequency Max320MHzRohs CompliantNo
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantNumber Of Gates-
Other names544-1446  
show all specifications
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Page 9/168

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PrevNext
Vertical migration means that you can migrate to devices whose
dedicated pins, configuration pins, and power pins are the same for a
given package across device densities.
Table 1–3. Total Number of Non-Migratable I/O Pins for Cyclone II Vertical Migration Paths
Vertical
144-Pin TQFP
Migration Path
EP2C5 to
4
EP2C8
EP2C8 to
—
EP2C15
EP2C15 to
—
EP2C20
EP2C20 to
EP2C35
EP2C35 to
—
EP2C50
EP2C50 to
—
EP2C70
Notes to
Table
1–3:
(1)
Vertical migration between the EP2C5F256 to the EP2C15AF256 and the EP2C5F256 to the EP2C20F256 devices is
not supported.
(2)
When migrating from the EP2C20F484 device to the EP2C50F484 device, a total of 39 I/O pins are non-migratable.
(3)
When migrating from the EP2C35F672 device to the EP2C70F672 device, a total of 56 I/O pins are non-migratable.
(4)
In addition to the one non-migratable I/O pin, there are 34 DQ pins that are non-migratable.
(5)
The pinouts of 484 FBGA and 484 UBGA are the same.
1
To ensure that your board layout supports migratable densities within
one package offering, enable the applicable vertical migration path
within the Quartus II software (go to Assignments menu, then Device,
then click the Migration Devices button). After compilation, check the
information messages for a full list of I/O, DQ, LVDS, and other pins that
are not available because of the selected migration path.
Cyclone II device package offerings and shows the total number of
non-migratable I/O pins when migrating from one density device to a
larger density device.
Altera Corporation
February 2008
256-Pin
484-Pin
208-Pin
FineLine BGA
FineLine BGA
PQFP
(1)
(2)
4
1
(4)
—
—
30
—
—
0
—
—
16
—
—
28
—
—
—
When moving from one density to a larger density, I/O pins are
often lost because of the greater number of power and ground
pins required to support the additional logic within the larger
device. For I/O pin migration across densities, you must cross
reference the available I/O pins using the device pin-outs for all
planned densities of a given package type to identify which I/O
pins are migratable.
Cyclone II Device Handbook, Volume 1
Introduction
672-Pin
484-Pin Ultra
FineLine BGA
FineLine BGA
(3)
—
—
—
—
0
—
—
—
—
(5)
28
28
28
28
Table 1–3
lists the
1–7

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