IC CYCLONE II FPGA 5K 256-FBGA

 

EP2C5F256C8

Manufacturer Part NumberEP2C5F256C8
DescriptionIC CYCLONE II FPGA 5K 256-FBGA
ManufacturerAltera
SeriesCyclone® II
EP2C5F256C8 datasheets

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Specifications of EP2C5F256C8

Number Of Logic Elements/cells4608Number Of Labs/clbs288
Total Ram Bits119808Number Of I /o158
Voltage - Supply1.15 V ~ 1.25 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case256-FBGA
Family NameCyclone® IINumber Of Logic Blocks/elements4608
# I/os (max)158Frequency (max)402.58MHz
Process Technology90nmOperating Supply Voltage (typ)1.2V
Logic Cells4608Ram Bits119808
Operating Supply Voltage (min)1.15VOperating Supply Voltage (max)1.25V
Operating Temp Range0C to 85COperating Temperature ClassificationCommercial
MountingSurface MountPin Count256
Package TypeFBGANo. Of Macrocells4608
Family TypeCyclone IINo. Of I/o's158
Clock ManagementPLLI/o Supply Voltage3.6V
Operating Frequency Max320MHzRohs CompliantNo
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantNumber Of Gates-
Other names544-1446  
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Table 5–53
devices.
Table 5–53. Cyclone II JTAG Timing Parameters and Values
Symbol
Parameter
TCK
t
clock period
J C P
TCK
t
clock high time
J C H
TCK
t
clock low time
J C L
t
JTAG port setup time
J P S U
t
JTAG port hold time
J P H
t
JTAG port clock to output
J P C O
t
JTAG port high impedance to valid output
J P Z X
t
JTAG port valid output to high impedance
J P X Z
t
Capture register setup time
J S S U
t
Capture register hold time
J S H
t
Update register clock to output
J S C O
t
Update register high impedance to valid output
J S Z X
t
Update register valid output to high impedance
J S X Z
Notes to
Table
5–53:
(1)
This information is preliminary.
(2)
This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For
1.8-V LVTTL/LVCMOS and 1.5-V LVCMOS, the JTAG port and capture register clock setup time is 3 ns and port
clock to output time is 15 ns.
1
f
For more information on JTAG, refer to the
Boundary-Scan Testing for Cyclone II Devices
Handbook.
Altera Corporation
February 2008
DC Characteristics and Timing Specifications
shows the JTAG timing parameters and values for Cyclone II
Min
(2)
(2)
(2)
(2)
(2)
Cyclone II devices must be within the first 17 devices in a JTAG
chain. All of these devices have the same JTAG controller. If any
of the Cyclone II devices are in the 18th position or after they will
fail configuration. This does not affect the SignalTap
analyzer.
Max
Unit
40
—
ns
20
—
ns
20
—
ns
5
—
ns
10
—
ns
—
13
ns
—
13
ns
—
13
ns
5
—
ns
10
—
ns
—
25
ns
—
25
ns
—
25
ns
®
II logic
IEEE 1149.1 (JTAG)
chapter in the Cyclone II
Cyclone II Device Handbook, Volume 1
5–65

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