EP2C5F256C8 | |
|---|---|
| Manufacturer Part Number | EP2C5F256C8 |
| Description | IC CYCLONE II FPGA 5K 256-FBGA |
| Manufacturer | Altera |
| Series | Cyclone® II |
| EP2C5F256C8 datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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Specifications of EP2C5F256C8 | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 4608 | Number Of Labs/clbs | 288 |
| Total Ram Bits | 119808 | Number Of I /o | 158 |
| Voltage - Supply | 1.15 V ~ 1.25 V | Mounting Type | Surface Mount |
| Operating Temperature | 0°C ~ 85°C | Package / Case | 256-FBGA |
| Family Name | Cyclone® II | Number Of Logic Blocks/elements | 4608 |
| # I/os (max) | 158 | Frequency (max) | 402.58MHz |
| Process Technology | 90nm | Operating Supply Voltage (typ) | 1.2V |
| Logic Cells | 4608 | Ram Bits | 119808 |
| Operating Supply Voltage (min) | 1.15V | Operating Supply Voltage (max) | 1.25V |
| Operating Temp Range | 0C to 85C | Operating Temperature Classification | Commercial |
| Mounting | Surface Mount | Pin Count | 256 |
| Package Type | FBGA | No. Of Macrocells | 4608 |
| Family Type | Cyclone II | No. Of I/o's | 158 |
| Clock Management | PLL | I/o Supply Voltage | 3.6V |
| Operating Frequency Max | 320MHz | Rohs Compliant | No |
| Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant | Number Of Gates | - |
| Other names | 544-1446 | ||
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PrevNext
Tables 5–50
devices. Cyclone II devices support LVDS receivers at data rates up to
805 Mbps, and LVDS transmitters at data rates up to 640 Mbps.
Table 5–50. LVDS Transmitter Timing Specification (Part 1 of 2)
–6 Speed Grade
Symbol
Conditions
Min
Typ
f
—
×10
10
H S C L K
(input
clock
×8
10
—
fre-
quency)
×7
10
—
×4
10
—
×2
10
—
×1
10
—
HSIODR
—
×10
100
×8
80
—
×7
70
—
×4
40
—
×2
20
—
—
×1
10
t
—
45
—
D U T Y
—
—
—
TCCS
—
—
—
(3)
Output
—
—
—
jitter
(peak to
peak)
t
20–80%
150
200
R I S E
Altera Corporation
February 2008
DC Characteristics and Timing Specifications
and
5–51
show the LVDS timing budget for Cyclone II
–7 Speed Grade
Max
Max
Max
Min
Typ
(1)
(2)
(1)
—
320
320
10
275
320
320
10
—
275
320
320
10
—
275
320
320
10
—
275
320
320
10
—
275
402.5 402.5
10
—
402.5 402.5
—
640
640
100
550
640
640
80
—
550
640
640
70
—
550
640
640
40
—
550
640
640
20
—
550
—
402.5 402.5
10
402.5 402.5
55
—
45
—
55
—
160
—
—
—
200
—
—
200
500
—
—
500
250
150
200
250
Cyclone II Device Handbook, Volume 1
–8 Speed Grade
Max
Max
Max
Min
Typ
(2)
(1)
(2)
—
155.5
320
10
320
(4)
(6)
155.5
320
10
—
320
(4)
(6)
155.5
320
10
—
320
(4)
(6)
320
10
—
155.5
320
(4)
(6)
320
10
—
155.5
320
(4)
(6)
10
—
402.5
402.5
(8)
(8)
—
640
100
311
550
(5)
(7)
640
80
—
311
550
(5)
(7)
640
70
—
311
550
(5)
(7)
640
40
—
311
550
(5)
(7)
640
20
—
311
550
(5)
(7)
—
10
402.5
402.5
(9)
(9)
—
45
—
55
—
312.5
—
—
—
363.6
—
—
200
—
—
550
(10)
150
200
250
(11)
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
ps
ps
ps
ps
5–61
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Altera Corporation | ||
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EP2C5T144I8 |
IC CYCLONE II FPGA 5K 144-TQFP | Altera |
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EP2C5T144C7 |
IC CYCLONE II FPGA 5K 144-TQFP | Altera |
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EP2C5Q208C7 |
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