IC CYCLONE II FPGA 5K 256-FBGA

 

EP2C5F256C8

Manufacturer Part NumberEP2C5F256C8
DescriptionIC CYCLONE II FPGA 5K 256-FBGA
ManufacturerAltera
SeriesCyclone® II
EP2C5F256C8 datasheets

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Specifications of EP2C5F256C8

Number Of Logic Elements/cells4608Number Of Labs/clbs288
Total Ram Bits119808Number Of I /o158
Voltage - Supply1.15 V ~ 1.25 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case256-FBGA
Family NameCyclone® IINumber Of Logic Blocks/elements4608
# I/os (max)158Frequency (max)402.58MHz
Process Technology90nmOperating Supply Voltage (typ)1.2V
Logic Cells4608Ram Bits119808
Operating Supply Voltage (min)1.15VOperating Supply Voltage (max)1.25V
Operating Temp Range0C to 85COperating Temperature ClassificationCommercial
MountingSurface MountPin Count256
Package TypeFBGANo. Of Macrocells4608
Family TypeCyclone IINo. Of I/o's158
Clock ManagementPLLI/o Supply Voltage3.6V
Operating Frequency Max320MHzRohs CompliantNo
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantNumber Of Gates-
Other names544-1446  
show all specifications
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Figure 2–25. Cyclone II IOE in Bidirectional I/O Configuration
io_clk[5..0]
Column
or Row
Interconect
OE
clkout
ce_out
aclr/prn
Chip-Wide Reset
sclr/preset
data_in1
data_in0
clkin
ce_in
The Cyclone II device IOE includes programmable delays to ensure zero
hold times, minimize setup times, or increase clock to output times.
A path in which a pin directly drives a register may require a
programmable delay to ensure zero hold time, whereas a path in which a
pin drives a register through combinational logic may not require the
delay. Programmable delays decrease input-pin-to-logic-array and IOE
input register delays. The Quartus II Compiler can program these delays
to automatically minimize setup time while providing a zero hold time.
Altera Corporation
February 2007
OE Register
PRN
D
Q
ENA
CLRN
Output Register
Output
PRN
Pin Delay
D
Q
ENA
Open-Drain Output
CLRN
Input Pin to
Input Register
Input Register Delay
or Input Pin to
PRN
Logic Array Delay
D
Q
ENA
CLRN
Cyclone II Device Handbook, Volume 1
Cyclone II Architecture
V
CCIO
Optional
PCI Clamp
V
CCIO
Programmable
Pull-Up
Resistor
Bus Hold
2–43

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