IC CYCLONE II FPGA 5K 256-FBGA

 

EP2C5F256C8

Manufacturer Part NumberEP2C5F256C8
DescriptionIC CYCLONE II FPGA 5K 256-FBGA
ManufacturerAltera
SeriesCyclone® II
EP2C5F256C8 datasheets

Availability: In stock

International delivery:

Warranty: 60 days

Shipping & payment terms

Added to cart

 

Specifications of EP2C5F256C8

Number Of Logic Elements/cells4608Number Of Labs/clbs288
Total Ram Bits119808Number Of I /o158
Voltage - Supply1.15 V ~ 1.25 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case256-FBGA
Family NameCyclone® IINumber Of Logic Blocks/elements4608
# I/os (max)158Frequency (max)402.58MHz
Process Technology90nmOperating Supply Voltage (typ)1.2V
Logic Cells4608Ram Bits119808
Operating Supply Voltage (min)1.15VOperating Supply Voltage (max)1.25V
Operating Temp Range0C to 85COperating Temperature ClassificationCommercial
MountingSurface MountPin Count256
Package TypeFBGANo. Of Macrocells4608
Family TypeCyclone IINo. Of I/o's158
Clock ManagementPLLI/o Supply Voltage3.6V
Operating Frequency Max320MHzRohs CompliantNo
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantNumber Of Gates-
Other names544-1446  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Page 61
62
Page 62
63
Page 63
64
Page 64
65
Page 65
66
Page 66
67
Page 67
68
Page 68
69
Page 69
70
Page 70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Page 61/168

Download datasheet (3Mb)Embed
PrevNext
Programmable Drive Strength
The output buffer for each Cyclone II device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL, LVCMOS,
SSTL-2 class I and II, SSTL-18 class I and II, HSTL-18 class I and II, and
HSTL-1.5 class I and II standards have several levels of drive strength that
you can control. Using minimum settings provides signal slew rate
control to reduce system noise and signal overshoot.
the possible settings for the I/O standards with drive strength control.
Table 2–16. Programmable Drive Strength (Part 1 of 2)
LVTTL (3.3 V)
LVCMOS (3.3 V)
LVTTL/LVCMOS (2.5 V)
LVTTL/LVCMOS (1.8 V)
Altera Corporation
February 2007
I
/I
OH
OL
I/O Standard
Top & Bottom I/O Pins
4
8
12
16
20
24
4
8
12
16
20
24
4
8
12
16
2
4
6
8
10
12
Cyclone II Device Handbook, Volume 1
Cyclone II Architecture
Table 2–16
shows
Note (1)
Current Strength Setting (mA)
Side I/O Pins
4
8
12
16
20
24
4
8
12
4
8
2
4
6
8
10
12
2–49