MC8641DVU1333JE Freescale Semiconductor, MC8641DVU1333JE Datasheet

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... Figure 1 shows the major functional units within the MPC8641 and MPC8641D. The major difference between the MPC8641 and MPC8641D is that there are two cores on the MPC8641D. © Freescale Semiconductor, Inc., 2009. All rights reserved. Document Number: MPC8641DEC Rev. 2, 07/2009 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 ...

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... Switch Fabric PCI Express Four-Channel DMA Controller Figure 1. MPC8641 and MPC8641D e600 Core Block e600 Core 1-Mbyte L2 Cache 32-Kbyte L1 Data Cache Platform Interface or Interface [ x1/x2/x4/x8 PCI Exp (4 GB/s) AND 1x/4x SRIO (2.5 GB/ [2-x1/x2/x4/x8 PCI Express (8 GB/S) ] Interface External Control Freescale Semiconductor ...

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... Four inbound windows plus a default window on serial RapidIO — Four outbound windows plus default translation for PCI Express — Eight outbound windows plus default translation for serial RapidIO with segmentation and sub-segmentation support MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Overview 3 ...

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... Supports 16 programmable interrupt and processor task priority levels — Supports 12 discrete external interrupts and 48 internal interrupts — Eight global high resolution timers/counters that can generate interrupts — Allows processors to interrupt each other with 32b messages MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... Programming model compatible with the original 16450 UART and the PC16550D • IEEE 1149.1-compatible, JTAG boundary scan • Available as 1023 pin Hi-CTE flip chip ceramic ball grid array (FC-CBGA) MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 2 C addressing mode Overview 2 C interface ...

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... Value –0 –0 –0 –0.3 to 1.21V V –0 –0.3 to 1.21V V –0.3 to 1.21V V –0.3 to 1.21V V –0 –0 –0 –0 –0 –0 –0 Freescale Semiconductor 2 — — — — — — — — ...

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... For details on order information and specific operating conditions for parts, see Section 21, “Ordering Information.” Table 2. Recommended Operating Conditions Characteristic Cores supply voltages Cores PLL supply SerDes Transceiver Supply (Ports 1 and 2) MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 1 (continued) Symbol ...

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... V 8 1.05 ± 1.10 ± 1.05 ± 1.10 ± 1.05 ± 2.5 V ± 125 1.8 V ± 3.3 V ± 165 2.5 V ± 125 3.3 V ± 165 2.5 V ± 125 3.3 V ± 165 _GV /2 ± GND GND GND 5,6 DD Freescale Semiconductor ...

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... This voltage is the input to the filter discussed in the voltage at the AV _Core n pin, which may be reduced from V DD MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Symbol T J _Core0 and V _Core1, they must be at the same nominal voltage and the ...

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... GND – 0.3 V GND – 0.7 V Not to Exceed 10% references clocks for various functional blocks as follows: Table and L/ CLK _ M/O/L/TV IN _Coren (See Table 2 for actual DD 2. The input voltage threshold scales with based receivers are simple CMOS I/O signal (nominally set REF Freescale Semiconductor ...

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... The recommended maximum ramp up time for power supplies is 20 milliseconds. The chronological order of power follows: 1. All power rails other than DDR I/O (Dn_GV MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 3. Output Drive Capability Programmable Output Impedance (Ω) ...

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... Power and Reset Sequencing details. MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev NOTE _PLAT, AV _PLAT rails must reach 90 Section 20.2.1, “PLL Power NOTE , Dn_MV ). DD REF NOTE , and Dn_MV (in REF type supplies DD , Dn_MV ) DD REF Freescale Semiconductor ...

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... SYSCLK must be driven only AFTER the power for the various power supplies is stable device sleep mode, the reset configuration signals for DRAM types (TSEC2_TXD[4],TSEC2_TX_ER) must be valid BEFORE HRESET is asserted. Figure 3. MPC8641 Power-Up and Reset Sequence MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor If 1 L/TV =2.5 V ...

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... C 49 23.9 30.0 o 105 C 34 23.9 30.0 o 105 C 34 23.9 30.0 o 105 C 34 16.2 21.8 o 105 C 25.0 _Core n ) and 65°C junction DD _Core n ) and maximum operating junction DD _Core n ) and maximum operating junction DD _Core n = 0.95 V and V _PLAT = 1. Freescale Semiconductor Notes ...

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... Local Bus, DUART, I management, JTAG and Miscellaneous I/O voltage. 5. These power numbers are for Part Number MC8641xxx1000NX only. V MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Supply Voltage (Volts) V _Core0/V _Core1 = 1 1500 MHz ...

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... Power Temperature (Watts 20.3 25.2 o 105 C 28 16.3 20.2 o 105 C 23 16.3 20.2 o 105 C 23 16.3 20.2 o 105 C 23 11.6 14.4 o 105 C 16.5 _Core n ) and 65°C junction DD _Core n ) and maximum operating junction DD _Core n ) and maximum operating junction DD _PLAT = 1. Freescale Semiconductor Notes ...

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... These clock sources intentionally add long-term jitter in order to diffuse the EMI spectral content. The jitter specification given in considers short-term (cycle-to-cycle) jitter only and the clock generator’s cycle-to-cycle output jitter MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Symbol Min V ...

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... Table 2. Min — — . There is no minimum RTC frequency; RTC may be MPX Symbol Min f — G125 t — G125 t — G125J Max Unit Notes 50 kHz 1 1 Table 8. Typical Max Unit Notes 125 ±100 — MHz ppm 8 — ns — 250 ps Freescale Semiconductor 3 — 1 ...

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... RapidIO interface frequency) × (Serial RapidIO link width) 4.5 Other Input Clocks For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC, see the specific section of this document. MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Symbol Min t /t G125H ...

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... MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev Min Max 100 — 3 — 100 — 4 — 2 — — 5 Table 12. PLL Lock Times Min Max — 100 — 50 Unit Notes μs — SYSCLKs 1 μs 2 SYSCLKs 1 SYSCLKs 1 SYSCLKs 1 Unit Notes μs 1 μs — Freescale Semiconductor ...

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... Table 14. DDR2 SDRAM Capacitance for D n _GV Parameter/Condition Input/output capacitance: DQ, DQS, DQS Delta input/output capacitance: DQ, DQS, DQS Note: 1. This parameter is sampled _GV (peak-to-peak) = 0.2 V. MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor (typ) = 2.5 V and DDR2 SDRAM Symbol Min D n _GV 1.71 DD 0.49 × ...

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... V 0.51 × _GV _MV + 0.04 V REF D n _GV + 0 _MV – 0.15 V REF μA 50 — mA — variations as measured at the receiver. . REF . DD (typ Max Unit Notes 0 _GVDD/2, = 25°C, V OUT REF Max Unit Note μA 500 1 Freescale Semiconductor Notes — — 4 — — ...

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... The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t determined by the following equation: t abs the absolute value of t CISKEW 3. Maximum DDR1 frequency is 400 MHz. MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Symbol Min V IL — _MV ...

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... MHz 1.48 400 MHz 1.95 t DDKHAX 600 MHz 1.10 533 MHz 1.48 400 MHz 1.95 t DDKHCS 600 MHz 1.10 533 MHz 1.48 400 MHz 1.95 t DISKEW Max Unit Notes 52 — — — ns — — — ns — — — Freescale Semiconductor ...

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... MCS[n] output hold with respect to MCK MCK to MDQS Skew MDQ/MECC/MDM output setup with respect to MDQS MDQ/MECC/MDM output hold with respect to MDQS MDQS preamble start MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 1 Symbol Min t DDKHCX 600 MHz 1.10 533 MHz 1 ...

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... DDR timing (DD) for the time t DDKHAS = ±125 ps. JIT NOTE Max Unit Notes 0 for outputs. Output hold time can memory clock reference (K) MCK symbolizes DDR DDKLDX describes the DDR DDKHMH can be DDKHMH follows DDKHMP Table 21 Freescale Semiconductor ...

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... DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH). Figure 6 shows the DDR SDRAM output timing diagram. MCK[n] MCK[n] ADDR/CMD Write A0 MDQS[n] MDQ[x] Figure 6. DDR SDRAM Output Timing Diagram MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor MCK[n] MCK[n] t MCK t DDKHMHmax) = 0.6 ns MDQS t DDKHMH(min) = –0.6 ns MDQS Figure 5 ...

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... Table 23. DUART AC Timing Specifications th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are Dn_GV / Ω Max Unit 0.8 V μA ±5 — V 0.2 V Table 1 and Table 2. Value Unit MPX clock/1,048,576 baud MPX clock/16 baud 16 — Freescale Semiconductor Notes 1,2 1,3 1,4 ...

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... Input high current ( MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management and Table 25. The potential applied to the input of a GMII, MII, TBI, into a GMII receiver powered from a 2.5-V supply). OH Symbol Min LV 3.135 ...

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... IN IN Symbol Min LV /TV 2.375 2. — 1. — — –15 IL and TV symbols referenced Unit Notes 3 μA Table 1 and Table 2. Max Unit Notes 1,2 2.625 V — V — 0.40 V — — V — 0.90 V — μA 1, 2,3 10 μA 3 — Table 1 and Table 2. Freescale Semiconductor ...

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... Fall time RX_CLK (80%–20%) RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK 1 ±100 ppm tolerance on RX_CLK frequency MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Restrictions.” NOTE Table 26 and of 3.3 V ± ...

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... FIR valid data t t FIRDV FIRDX Figure 9. FIFO Receive AC Timing Diagram of 3.3 V ± 5% and 2.5 V ± 5%. DD Symbol t GTKHDV t GTKHDX t GTXR t t FITF FITR t FIRR t FIRF 1 Min Typ Max 2.5 — — 0.5 — 5.0 2 — — 1.0 Freescale Semiconductor Unit ...

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... RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise time (20%-80%) MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management of 3.3 V ± 5% and 2.5 V ± 5%. DD ...

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... GMII (G) receive (RX) clock. For rise and fall times, the latter GRX = 50 Ω Figure 11. eTSEC AC Test Load t GRX t t GRXF GRXH t GRDXKH t GRDVKH Figure 12. GMII Receive AC Timing Diagram Min Typ Max — — 1.0 symbolizes GMII GRDVKH Ω GRXR Freescale Semiconductor Unit ns clock ...

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... R (rise (fall). 2. Guaranteed by design. Figure 13 shows the MII transmit AC timing diagram. TX_CLK TXD[3:0] TX_EN TX_ER MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management of 3.3 V ± 5 Symbol 2 t MTX ...

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... Valid Data t MRDVKH Figure 15. MII Receive AC Timing Diagram Min Typ Max — 400 — — 40 — 35 — 65 10.0 — — 10.0 — — 1.0 — 4.0 1.0 — 4.0 symbolizes MII receive MRDVKH clock reference (K) MRX Ω MRXR t MRDXKL Freescale Semiconductor Unit ...

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... TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: TTX R (rise (fall). 2. Guaranteed by design. Figure 16 shows the TBI transmit AC timing diagram. GTX_CLK TCG[9:0] MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management of 3.3 V ± 5% and 2.5 V ± 5 Symbol t TTKHDV t ...

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... Figure 17. TBI Receive AC Timing Diagram Min Typ Max — 16.0 — 7.5 — 8.5 40 — 60 2.5 — — 1.5 — — 0.7 — 2.4 0.7 — 2.4 symbolizes TBI receive TRDVKH clock reference (K) going TRX t TRXR Valid Data t TRDXKH t TRDXKH t TRDVKH Freescale Semiconductor Unit ...

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... At recommended operating conditions with L/TV Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management of 3.3 V ± 5% and 2.5 V ± 5%. DD Symbol ...

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... TBI (T) receive (RX) clock. Note also that the RGT t RGTH t SKRGT TXD[8:5] TXD[3:0] TXD[7:4] TXD[9] TXD[4] TXEN TXERR RXD[8:5] RXD[3:0] RXD[7:4] t SKRGT RXD[4] RXD[9] RXERR RXDV Typ Max Unit 8.0 8 — 0.75 ns — 0. the lowest speed transitioned RGT t RGT t SKRGT t SKRGT Freescale Semiconductor ...

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... R (rise (fall). Figure 20 shows the RMII transmit AC timing diagram. REF_CLK TXD[1:0] TX_EN TX_ER Figure 20. RMII Transmit AC Timing Diagram MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Table 36. of 3.3 V ± 5 Symbol t ...

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... Valid Data t RMRDV Figure 22. RMII Receive AC Timing Diagram Min Typ Max 15.0 20.0 25 — — 250 1.0 — 2.0 1.0 — 2.0 4.0 — — 2.0 — — symbolizes MII receive MRDVKH clock reference (K) going MRX Ω RMRR t RMRDX Freescale Semiconductor Unit ...

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... MDC frequency MDC period MDC clock pulse width high MDC to MDIO valid MDC to MDIO delay MDIO to MDC setup time MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Ethernet Management Interface Electrical Characteristics “Section 8, “Ethernet: Enhanced Three-Speed Table 38. Symbol Min OV 3 ...

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... For MDC = 50 Ω Figure 23. eTSEC AC Test Load NOTE t MDC t t MDCH MDCF t MDDVKH t MDDXKH t MDKHDX Typ Max Unit — — ns — — for outputs. For example, t MDKHDX Ω MDCR Freescale Semiconductor Notes — ...

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... LALE output transition to LAD/LDP output transition (LATCH hold time) Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Symbol Min ...

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... LSYNC_IN for PLL enabled or internal local bus clock for PLL Ω Figure 25. Local Bus AC Test Load 1 Min Max Unit — 2.3 ns 0.7 — ns 0.7 — ns — 2.5 ns — 2.5 ns for outputs. For example, t LBIXKH1 clock reference (K) goes LBK clock reference ( LBK LBOTOT Ω Freescale Semiconductor Notes 3 — ...

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... Local bus duty cycle Internal launch/capture clock to LCLK delay Input setup to local bus clock (except LGTA/LUPWAIT) LGTA/LUPWAIT input setup to local bus clock Input hold from local bus clock (except LGTA/LUPWAIT) MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor t LBIVKH1 t LBIVKH2 t ...

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... LBKLOZ1 t — 0.2 LBKLOZ2 (First two letters of functional block)(signal)(state) (reference)(state) for outputs. For example, t LBIXKH1 clock reference (K) goes high (H), in this case LBK clock reference ( high (H), with respect LBK Unit Notes symbolizes local bus Freescale Semiconductor ...

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... LGTA/LUPWAIT signal, which is captured at the rising edge of the internal clock. MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor t LBKHKT t LBKLOV1 ...

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... LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 28. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (clock ratio of 4) (PLL Enabled) MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev LBKHOV1 LBKHOZ1 t LBIVKH2 t LBIVKH1 t t LBKHOV1 LBKHOZ1 t LBIXKH2 t LBIXKH1 Freescale Semiconductor ...

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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 29. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (clock ratio of 4) MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor t LBKLOV1 t LBIVKH1 (PLL Bypass Mode) Local Bus ...

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... LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 30. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (clock ratio 16) MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev LBKHOV1 LBKHOZ1 t LBIVKH2 t LBIVKH1 t t LBKHOV1 LBKHOZ1 (PLL Enabled) t LBIXKH2 t LBIXKH1 Freescale Semiconductor ...

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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 31. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (clock ratio 16) MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor t LBKLOV1 t LBIVKH1 (PLL Bypass Mode) Local Bus t ...

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... Boundary-scan data t JTKLDV TDO t JTKLOV Min Max Unit 0 0.8 V μA — ±5 – 0.2 — V — 0.2 V Table 1 and Table 2. Figure 33 through Figure 1 Min Max Unit 0 33.3 MHz 30 — — — — 0 — — 25 — Freescale Semiconductor 35. Notes — — — ...

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... AC test load for TDO and the boundary-scan outputs. Output Figure 32. AC Test Load for the JTAG Interface Figure 33 provides the JTAG clock input timing diagram. JTAG External Clock MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 3). 2 Symbol Boundary-scan data t JTKLDX ...

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... Figure 35. Boundary-Scan Timing Diagram 2 C interfaces. 2 Table 45 Electrical Characteristics of 3.3 V ± 5%. DD Symbol Min 0.7 × –0 I2KHKL JTDXKH Input Data Valid Output Data Valid 2 C interfaces of the MPC8641. Max Unit 0.3 × 0.2 × μA –10 10 Freescale Semiconductor Notes — — ...

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... Set-up time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Electrical Characteristics (continued) of 3.3 V ± 5%. DD ...

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... C AC Test Load Min Max 0.2 × OV — DD symbolizes I I2DVKH clock reference (K) going to the I2C symbolizes I I2PVKH 2 C SCL clock frequency 133 MHz 0x00 384 346 KHz 2 C Frequency Divider Ratio ) of the SCL signal. I2CL Ω L Freescale Semiconductor Unit timing 2 C clock I2C ...

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... SDn_RX each have a peak-to-peak swing of A – B Volts. This is also referred as each signal wire’s Single-Ended Swing. 2. Differential Output Voltage, V The Differential Output Voltage (or Swing) of the transmitter, V the two complimentary output voltages negative. 3. Differential Input Voltage, V MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 2 C bus I2DVKH I2KHKL t ...

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... B)| Volts, which is twice of differential swing in DIFFp = 2*|V |. TX-DIFFp-p OD Figure 47 cm Differential Swing, VID or VOD = Differential Peak Voltage, VDIFFp = | Differential Peak-Peak Voltage, VDIFFpp = 2*VDIFFp (not shown defined as the difference of the ID The V value can be either positive example for differential waveform. cm_out Freescale Semiconductor = ...

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... If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 Ω to SGND DC exceeds the maximum input current limitations, then it must be AC-coupled off-chip. MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor is 500 mV in one phase and –500 mV in the other 500 mV. The peak-to-peak differential voltage (V ...

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... Vmin to Vmax) with SDn_REF_CLK either left unconnected or tied to ground. MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev Ω Input Amp 50 Ω Section 13.2.1, “SerDes Reference Figure 41 shows the SerDes reference clock input Freescale Semiconductor ...

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... Figure 41. Differential Reference Clock Input DC Requirements (External AC-Coupled) 400 mV < _REF_CLK Input Amplitude < 800 _REF_CLK SD n _REF_CLK Figure 42. Single-Ended Reference Clock Input DC Requirements MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) Figure 42 shows Vmax < 800 mV 100 mV < Vcm < 400 mV Vmin > ...

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... They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended ...

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... SerDes reference clock connection reference circuits for LVPECL type clock driver. Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor SD n _REF_CLK 100 Ω differential PWB trace ...

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... Clock Driver CLK_Out R1 Figure 45. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only) MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev _REF_CLK 10nF 10nF R2 100 Ω differential PWB trace 10nF _REF_CLK Figure 45 MPC8641D 50 Ω SerDes Refer. CLK Receiver 50 Ω Freescale Semiconductor ...

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... CLK Driver Chip 33 Ω Clock Driver CLK_Out Figure 46. Single-Ended Connection (Reference Only) MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Total 50 Ω. Assume clock driver’s output impedance is about 16 Ω _REF_CLK 100 Ω differential PWB trace SD n _REF_CLK Ω ...

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... MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev SRDS1 or XV SRDS2 = 1.1V ± 5% and 1.05V ± 5%. DD_ DD_ Symbol Rise Edge Rate Fall Edge Rate Rise-Fall Matching Figure 47. Figure 48. Min Max Unit Notes 1.0 4.0 V/ 1.0 4.0 V/ +200 mV 2 — –200 mV 2 — Freescale Semiconductor ...

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... PCI Express This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8641. MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor SD n _REF_CLK SD n _REF_CLK SD1_RX n or ...

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... Ratio of the V bits after a transition divided by the V first bit after a transition. See Note 2. Typical Max Units Notes 10 — ns — — 100 ps — — — Comments = 2*|V – See Note 2. TX-D+ TX-D- of the second and following TX-DIFFp-p of the TX-DIFFp-p Freescale Semiconductor ...

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... Common Mode Voltage I TX Short Circuit TX-SHORT Current Limit T Minimum time TX-IDLE-MIN spent in Electrical Idle MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Min Nom Max Units 0.70 — — UI The maximum Transmitter jitter can be derived as T TX-MAX-JITTER See Notes 2 and 3. — ...

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... Downstream and one Upstream Port. See Note 7. TX-EYE-MEDIAN-to-MAX-JITTER built-in. An external AC Coupling capacitor is required. TX Comments Figure 52 and measured over Figure 50) = 0.30 UI for the TX-JITTER-MAX median is less than half of the total Figure 52). Note that the series Figure 52 for both V and V . TX-D+ TX-D- Freescale Semiconductor ...

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... UI interval with a fit algorithm using a minimization merit function (that is, least squares and median deviation fits). Figure 50. Minimum Transmitter Timing and Voltage Output Compliance Specifications MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor is specified using the passive compliance/test measurement load (see NOTE PCI Express ...

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... RX DC Differential mode impedance. See Note 5 Required well as D– DC Impedance (50 ± 20% tolerance). See Notes 2 and 5. Required well as D– DC Impedance when the Receiver terminations do not have power. See Note 2*|V –V RX-IDLE-DET-DIFFp-p RX-D+ RX-D- Measured at the package pins of the Receiver Freescale Semiconductor = |/2 | ...

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... Receiver is due to traces internal to the package as well as silicon parasitic characteristics which cause the real PCI Express component to vary in impedance from the compliance/test measurement load. The input Receiver eye diagram is implementation specific and is not specified. RX component designer should MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Min Nom Max Units — ...

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... D+ and D– not being exactly matched in length at the package pin boundary. MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev NOTE Figure 52). Note that the series capacitors, C Figure NOTE Ω to ground for , are TX 52. Freescale Semiconductor ...

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... To ensure interoperability between drivers and receivers of different vendors and technologies, AC coupling at the receiver input must be used. 15.1 DC Requirements for Serial RapidIO SD n _REF_CLK and SD n _REF_CLK For more information, see Section 13.2, “SerDes Reference Clocks.” MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Serial RapidIO 77 ...

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... Min Typical Max Units — 10(8) — — — 80 –40 — 40 Figure 53 shows how the signals are defined. The figures show , is defined defined Differential Peak-Peak = 2 * (A-B) Comments applies only to serial RapidIO with 125-MHz reference clock ps — ps — – – Freescale Semiconductor ...

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... It is recommended that the timing skew at the output of an LP-Serial transmitter between the two signals that comprise a differential pair not exceed 1.25 GB 2.50 GB and 3.125 GB. MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Serial RapidIO 79 ...

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... UI p-p — UI p-p — ps Skew at the transmitter output between lanes of a multilane link ps +/– 100 ppm Unit Notes Volts Voltage relative to COMMON of either signal comprising a differential pair mV p-p — UI p-p — UI p-p — Freescale Semiconductor ...

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... Table 56. Long Run Transmitter AC Timing Specifications—2.5 GBaud Characteristic Output Voltage, Differential Output Voltage Deterministic Jitter Total Jitter Multiple output skew Unit Interval MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Range Symbol Min Max S — 1000 MO UI ...

Page 82

... A B Time in UI Unit Notes Volts Voltage relative to COMMON of either signal comprising a differential pair mV p-p — UI p-p — UI p-p — ps Skew at the transmitter output between lanes of a multilane link ps +/– 100 ppm 1-B 1-A Freescale Semiconductor 1 ...

Page 83

... Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor V min V ...

Page 84

... Figure 55. The sinusoidal jitter component Unit Notes mV p-p Measured at receiver UI p-p Measured at receiver UI p-p Measured at receiver UI p-p Measured at receiver ns Skew at the receiver input between lanes of a multilane link — — ps +/– 100 ppm Figure 55. The sinusoidal jitter component Freescale Semiconductor ...

Page 85

... Receiver Input Compliance Mask shown in the receiver test signal is measured at the input pins of the receiving device with the device replaced with a 100 Ω +/– 5% differential resistive load. MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Frequency (Table 59, Table ...

Page 86

... Continuous Jitter Test Pattern (CJPAT) defined in Annex 48A of IEEE 802.3ae. All lanes of the LP-Serial MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev Time (UI) Figure 56. Receiver Input Compliance Mask V min (mV) V DIFF DIFF 100 100 100 1-B 1-A max (mV) A (UI) B (UI) 800 0.275 0.400 800 0.275 0.400 800 0.275 0.400 Freescale Semiconductor 1 ...

Page 87

... MHz and a 20 dB/decade roll-off below this. The required sinusoidal jitter specified in Section 8.6 is then added to the signal and the test load is replaced by the receiver being tested. MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Serial RapidIO -12 . ...

Page 88

... Ball diameter (typical ) 1 High-coefficient of thermal expansion 2 Typical ball diameter is before reflow MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev 12.1 mm × 14 × 1023 caps; 100 nF each 1 HX) 2.97 mm 2.47 mm 89.5% Pb 10. VU) 2.77 mm 2.27 mm 95.5% Sn 4.0% Ag 0.5% Cu 0.60 mm Freescale Semiconductor ...

Page 89

... The mechanical dimensions and bottom surface nomenclature of the MPC8641D (dual core) and MPC8641 (single core) high-lead FC-CBGA (package option: HCTE HX) and lead-free FC-CBGA (package option: HCTE VU) are shown respectfully in Figure 57. MPC8641D High-Head FC-CBGA Dimensions MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Figure 57 and Figure 58. ...

Page 90

... VDD_Core1 (R16, R18, R20, T17, T19, T21, T23, U16, U18, U22, V17, V19, V21, V23, W16, W18, W20, W22, Y17, Y19, Y21, Y23, AA16, AA18, AA20, AA22, AB23, AC24) and SENSEVDD_Core1 (U20). MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev NOTES for Figure 57 Freescale Semiconductor ...

Page 91

... Figure 58. MPC8641D Lead-Free FC-CBGA Dimensions MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Package 91 ...

Page 92

... I/O D1_GV DD I/O D1_GV DD O D1_GV DD I/O D1_GV DD I/O D1_GV DD O D1_GV DD O D1_GV DD O D1_GV DD O D1_GV DD O D1_GV DD O D1_GV DD O D1_GV DD O D1_GV DD Freescale Semiconductor Notes — — — — — — — — — — — 23 — ...

Page 93

... SD1_TX[0:7] L27, M25, N27, P25, R27, T25, U27, V25 SD1_RX[0:7] J32, K30, L32, M30, T30, U32, V30, W32 MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Package Pin Number DDR Port 1 DDR Memory Interface 2 Signals DDR Port 2 High Speed I/O Interface 1 (SERDES 1) ...

Page 94

... Pin Type Power Supply Analog SV DD Analog Analog Analog Analog SV DD Analog Analog Analog SV DD — — — — — — — — 5 Freescale Semiconductor Notes — — — 13, 17 13, 18 13, 17 13, 18 — 34 — 32, 35 — 35 — — 13, 17 13, 18 13 ...

Page 95

... AE21 TSEC2_RXD[0:7]/ AL22, AK22, AM21, AH20, AG20, AF20, GPIN[8:15] AF23, AF22 TSEC2_RX_DV AC19 TSEC2_RX_ER AD21 MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Package Pin Number 5 eTSEC Port 1 Signals 5 eTSEC Port 2 Signals Signal Listings Pin Type Power Supply I ...

Page 96

... AF14 TSEC4_RX_CLK AG13 MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev Package Pin Number 5 eTSEC Port 3 Signals 5 eTSEC Port 4 Signals Pin Type Power Supply I I Freescale Semiconductor Notes 40 6 — — — — — — — — — — — 40 ...

Page 97

... DMA_DREQ[2]/LCS[5] B23 DMA_DREQ[3]/IRQ[9] B30 DMA_DACK[0:1] D32, F30 DMA_DACK[2]/LCS[6] E23 DMA_DACK[3]/IRQ[10] C30 MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Package Pin Number 5 Local Bus Signals 5 DMA Signals Signal Listings Pin Type Power Supply I/O OV ...

Page 98

... MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev Package Pin Number Programmable Interrupt Controller Signals 5 DUART Signals Signals System Control Signals Pin Type Power Supply Freescale Semiconductor Notes — — 12, S4 — — — — — — — — 12, S4 — 12, S4 — 10, 25 ...

Page 99

... AL25, AL24, AK26, AK25, AM26, AF26, TSEC1_RXD[0:7] AH24, AG25 GPOUT[8:15]/ AB20, AJ23, AJ22, AD19, AH23, AH21, TSEC2_TXD[0:7] AG22, AG21 MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Package Pin Number 5 Debug Signals Power Management Signals System Clocking Signals 5 Test Signals ...

Page 100

... Pin Type Power Supply Thermal — Thermal — _Core0 — _Core1 — 12,31, S1 — — 12, 31, S3 _PLAT — — D1_GV DD supply 2.5 - DDR 1.8 DDR2 D2_GV DD supply 2 DDR 1 DDR2 2.5/3.3 V voltage Freescale Semiconductor Notes 10 — — — — — — ...

Page 101

... A20 DD AV _SRDS1 P32 DD AV _SRDS2 AF32 DD MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Package Pin Number TSEC3 and TSEC4 I/O Transceiver Power Supply Power Supply for SerDes Power Supply for SerDes Core 0 voltage Core 1 voltage ...

Page 102

... Ground pins for Ground pins for XV Reset Configuration Signals Pin Type Power Supply GND — — _SRDS1 DD — _SRDS2 DD — — _SRDS — — — — — — — Freescale Semiconductor Notes — — — — — — 21 — — — — 38 ...

Page 103

... J21 LA[28:31]/ K21, G22, F24, G21 cfg_sys_pll[0:3] LGPL[3], K20, LGPL[5]/ J19 cfg_boot_seq[0:1] D1_MSRCID[0]/ F15 cfg_mem_debug D1_MSRCID[1]/ K15 cfg_ddr_debug MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Package Pin Number Signal Listings Pin Type Power Supply — — — ...

Page 104

... PHY from seeing a valid Transmit Enable before it is actively driven. MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 104 Package Pin Number . DD Pin Type Power Supply _PLAT and is hence considered as the DD Freescale Semiconductor Notes ...

Page 105

... The minimum e600 core frequency is based on the minimum platform clock frequency of 400 MHz. MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Package Pin Number Restrictions” for clock speed limitations for this pin when used in FIFO mode. ...

Page 106

... Min Max 400 500-600 and Section 18.3, “e600 to MPX clock PLL Ratio,” Maximum Processor Core Frequency 1000, 1250, 1333, 1500MHz Min Max 25 133 Table 68: Freescale Semiconductor Unit Notes MHz 1, 2 Unit Notes MHz 1, 2 Unit Notes MHz 1 ...

Page 107

... LDP[0:3], LA[27](cfg_core_pll[0:4] - reset config name) at power up, as shown in Table 69. Binary Value of LDP[0:3], LA[27] Signals e600 core: MPX Clock Ratio 18.4 Frequency Options MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 68. MPX:SYSCLK Ratio MPX:SYSCLK Ratio 0000 0001 0010 0011 ...

Page 108

... MHz MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 108 Section 17, “Signal SYSCLK (MHz 100 111 Platform/MPX Frequency (MHz) 400 500 555 400 500 600 533 600 Listings,” because reset 133 167 1 400 500 533 Freescale Semiconductor ...

Page 109

... Occasionally the spring clip is attached to soldered hooks plastic backing structure. Screw and spring arrangements are also frequently used. MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 71. Package Thermal Characteristics Section 19.2.4, “Temperature Diode,” ...

Page 110

... Millennium Electronics (MEI) Loroco Sites 671 East Brokaw Road San Jose, CA 95112 Internet: www.mei-thermal.com MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 110 HCTE FC-CBGA Package Heat Sink Heat Sink Clip Thermal Printed-Circuit Board 603-224-9988 781-769-2800 408-749-7601 888-732-6100 408-436-8770 Freescale Semiconductor ...

Page 111

... Because the silicon thermal resistance is quite small, the temperature drop in the silicon may be neglected for a first-order analysis. Thus the thermal interface material and the heat sink conduction/convective thermal resistances are the dominant terms. MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 800-522-6752 603-635-5102 Table ...

Page 112

... There are several commercially available thermal interfaces and adhesive materials provided by the following vendors: MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 112 Silicone Sheet (0.006 in.) Bare Joint Fluoroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease Contact Pressure (psi Freescale Semiconductor ...

Page 113

... An electronic cabinet inlet-air temperature (T may range from The air temperature rise within a cabinet ( The thermal resistance of the thermal interface material (R MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 800-347-4572 781-935-4850 800-248-2481 ...

Page 114

... MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 114 package R θ obtained (0.1 C/W + 0.2 C/W + θ the xy-plane and 5.3 W/(m • = 0.1, and a typical power consumption ) × 43 Figure 62. Four cuboids are used Section the • the thickness • Freescale Semiconductor ...

Page 115

... V > 0. < 0. Operating range 2–300 μA Diode leakage < 125°C Ideality factor over 5–150 μA at 60° 1.0275 MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Value Unit Temperature dependent 5.3 W/(m • K) 13.5 W/(m • K) 13.5 5.3 0.034 W/(m • ...

Page 116

... The above simplifies to the following 1.986 × 10 –4 × – Solving for T, the equation becomes: V – __________ nT = 1.986 × 10 –4 MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 116 is flowing H is flowing L –19 C) –23 Joules/K) Freescale Semiconductor ...

Page 117

... V _PLAT DD Figure 63. MPC8641 PLL Power Supply Filter Circuit (for platform and Local Bus) MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Section 18.2, “MPX to SYSCLK PLL Ratio.” 2.2 µF 2.2 µF Low ESL Surface Mount Capacitors ...

Page 118

... Low ESL Surface Mount Capacitors GND _Core1 should be tied to ground with a weak 2.2 µF 2.2 µF GND Figure 65. SerDes PLL Power Supply Filter . DD DD type and supplies refer to DD _Core0/1 AV _SRDS n DD 0.003 µF power plan. Section 2.2, “Power Up/Down Freescale Semiconductor ...

Page 119

... Note that these power supplies can only be powered up again at reset for functionality to occur on the DDR port. Power supplies for other functional buses should remain powered. MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor , Dn_GV ...

Page 120

... Clock not required) Termination.” Enabled through POR input SerDes port is enabled Partial termination may be required (Reference Clock is required) SerDes port is disabled after software disables port Same termination requirements as when the port is enabled through POR input (Reference Clock is required) Freescale Semiconductor ...

Page 121

... SENSEV _Core1 and needs to be connected to ground with a weak (2- Likewise, AV _Core1 needs to be pulled to ground as shown in DD MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor NOTE Section 17, “Signal Listings.” Ω resistor: SD1_IMP_CAL_TX, Ω pull down resistor to prevent PHY from seeing a valid ...

Page 122

... Table 73. Impedance Characteristics DUART, Control, PCI Express Management 43 Target 25 Target 43 Target 25 Target Table 105°C. j Section 16.2, “Mechanical Dimensions of Section 17, “Signal /2 (see Figure DD and R are designed to be close to each SW2 SW1 DDR DRAM Symbol Unit 20 Target Target Freescale Semiconductor Listings.” DD 66). The , DD ...

Page 123

... The arrangement shown in Figure 67 while ensuring that the target can drive HRESET as well. MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor allows the COP port to independently assert HRESET or TRST, System Design Information 123 ...

Page 124

... Figure 68, can be duplicated for each processor. The Figure 69. Please consult with your tool vendor to COP_TDO COP_TDI 3 4 COP_TRST COP_VDD_SENSE COP_TCK 7 8 COP_CHKSTP_IN COP_TMS KEY 13 No pin GND 15 16 Figure 67. COP Connector Physical Pinout Figure 67; consequently, many different Freescale Semiconductor ...

Page 125

... This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed. Figure 68. JTAG/COP Interface Connection for one MPC8641 device MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor COP_HRESET COP_SRESET 5 COP_TRST 10 Ω ...

Page 126

... TDI MPC8641 SRESET0 SRESET1 3 HRESET OV DD 10kΩ 4 TRST 5 CHKSTP_OUT CHKSTP_IN TMS 3 TCK TDO TDI MPC8641 SRESET0 SRESET1 HRESET 4 TRST CHKSTP_OUT CHKSTP_IN TMS TCK TDO Freescale Semiconductor 4 4 ...

Page 127

... Part Number MC8641xxx1000NX is our low V MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 74. Part Numbering Nomenclature xx nnnn ...

Page 128

... Max DDR = 500 MHz Core Voltage = 1.05 volts Single core Max CPU speed = 1000 MHz, Max DDR = 400 MHz Core Voltage = 1.05 volts Single core Max CPU speed = 1000 MHz, Max DDR = 500 MHz Core Voltage = 0.95 volts Table 74. Freescale Semiconductor ...

Page 129

... Removed the statement “Note that core processor speed of 1500 MHz is only available for the MPC8641D (dual core)” from Note 2 in MPC8641D (dual core) and MPC8641 (single core). • Added Note 07/2008 • Initial Release MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Figure 70. MC8641x xxnnnnxx TWLYYWW MMMMMM YWWLAZ 8641D Table 76 ...

Page 130

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...