MC8641DVU1333JE Freescale Semiconductor, MC8641DVU1333JE Datasheet - Page 68

• Manufacturer Part Number: MC8641DVU1333JE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8641DVU1333JE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.333GHz
• Voltage: 1.05V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Family Name: MPC8xxx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 1.333GHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.05V
• Operating Supply Voltage (max): 1.1V
• Operating Supply Voltage (min): 1V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1023
• Package Type: FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

High-Speed Serial Interfaces (HSSI)
13.2.4
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50 Ω to match the
transmission line and reduce reflections which are a source of noise to the system.
Table 47
68
At recommended operating conditions with XV
Rising Edge Rate
Falling Edge Rate
Differential Input High Voltage
Differential Input Low Voltage
Rising edge rate (SD n _REF_CLK) to falling edge rate
(SD n _REF_CLK) matching
Notes:
1. Measurement taken from single ended waveform.
2. Measurement taken from differential waveform.
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SD n _REF_CLK minus SD n _REF_CLK). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered
on the differential zero crossing. See
4. Matching applies to rising edge rate for SD n _REF_CLK and falling edge rate for SD n _REF_CLK. It is measured using a 200
mV window centered on the median cross point where SDn_REF_CLK rising meets SD n _REF_CLK falling. The median cross
point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate
of SD n _REF_CLK should be compared to the Fall Edge Rate of SD n _REF_CLK, the maximum allowed difference should not
exceed 20% of the slowest edge rate. See
SD n _REF_CLK
SD n _REF_CLK
V
V
IH
IL
= +200 mV
= -200 mV
describes some AC parameters common to PCI Express and Serial RapidIO protocols.
0.0 V
minus
AC Requirements for SerDes Reference Clocks
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Figure 47. Differential Measurement Points for Rise and Fall Time
Parameter
Table 47. SerDes Reference Clock Common AC Parameters
Figure
DD_
Figure
SRDS1 or XV
47.
48.
DD_
SRDS2 = 1.1V ± 5% and 1.05V ± 5%.
Rise Edge Rate
Fall Edge Rate
Matching
Rise-Fall
Symbol
V
V
IH
IL
+200
Min
1.0
1.0
—
—
–200
Max
4.0
4.0
20
Freescale Semiconductor
V/ns
V/ns
Unit
mV
mV
%
Notes
2, 3
2, 3
1, 4
2
2