MC8641DVU1333JE Freescale Semiconductor, MC8641DVU1333JE Datasheet - Page 72

• Manufacturer Part Number: MC8641DVU1333JE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8641DVU1333JE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.333GHz
• Voltage: 1.05V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Family Name: MPC8xxx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 1.333GHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.05V
• Operating Supply Voltage (max): 1.1V
• Operating Supply Voltage (min): 1V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1023
• Package Type: FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

PCI Express
72
T
T
RL
RL
Z
Z
L
C
T
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in
3. A T
4. The Transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode
5. Measured between 20-80% at transmitter package pins into a test load as shown in
6. See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a
7. See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a
8. MPC8641D SerDes transmitter does not have C
TX-SKEW
TX-IDLE-SET-TO-IDLE
TX-IDLE-TO-DIFF-DATA
TX-DIFF-DC
TX-DC
crosslink
TX
TX-DIFF
TX-CM
any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in
Transmitter collected over any 250 consecutive TX UIs. The T
TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed
to the averaged time value.
return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement
applies to all valid input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the D+ and
D- line (that is, as measured by a Vector Network Analyzer with 50 ohm probes—see
capacitors C
TX-EYE
Symbol
= 0.70 UI provides for a total sum of deterministic and random jitter budget of T
TX
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
is optional for the return loss measurement.
Table 49. Differential Transmitter (TX) Output Specifications (continued)
Maximum time to
transition to a
valid Electrical
idle after sending
an Electrical Idle
ordered set
Maximum time to
transition to valid
TX specifications
after leaving an
Electrical idle
condition
Differential
Return Loss
Common Mode
Return Loss
DC Differential
TX Impedance
Transmitter DC
Impedance
Lane-to-Lane
Output Skew
AC Coupling
Capacitor
Crosslink
Random
Timeout
Parameter
Min
12
80
40
75
—
—
—
6
0
Nom
100
TX
—
—
—
—
—
—
—
—
built-in. An external AC Coupling capacitor is required.
500 +
Max
2 UI
120
20
20
—
—
—
—
—
TX-EYE-MEDIAN-to-MAX-JITTER
Units
ms
dB
dB
nF
ps
UI
UI
Ω
Ω
After sending an Electrical Idle ordered set, the
Transmitter must meet all Electrical Idle Specifications
within this time. This is considered a debounce time
for the Transmitter to meet Electrical Idle after
transitioning from L0.
Maximum time to meet all TX specifications when
transitioning from Electrical Idle to sending differential
data. This is considered a debounce time for the TX to
meet all TX specifications after leaving Electrical Idle
Measured over 50 MHz to 1.25 GHz. See Note 4
Measured over 50 MHz to 1.25 GHz. See Note 4
TX DC Differential mode Low Impedance
Required TX D+ as well as D- DC Impedance during
all states
Static skew between any two Transmitter Lanes within
a single Link
All Transmitters shall be AC coupled. The AC coupling
is required either within the media or within the
transmitting component itself. See Note 8.
This random timeout helps resolve conflicts in
crosslink configuration by eventually resulting in only
one Downstream and one Upstream Port. See Note 7.
Figure 52
Figure
median is less than half of the total
TX-JITTER-MAX
Comments
Figure
52). Note that the series
Figure 52
for both V
Freescale Semiconductor
50)
and measured over
= 0.30 UI for the
TX-D+
and V
TX-D-
.