MC8641DVU1333JE Freescale Semiconductor, MC8641DVU1333JE Datasheet - Page 26

• Manufacturer Part Number: MC8641DVU1333JE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8641DVU1333JE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.333GHz
• Voltage: 1.05V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Family Name: MPC8xxx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 1.333GHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.05V
• Operating Supply Voltage (max): 1.1V
• Operating Supply Voltage (min): 1V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1023
• Package Type: FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

DDR and DDR2 SDRAM
26
At recommended operating conditions.
MDQS epilogue end
Note:
1. The symbols used for timing specifications follow the pattern of t
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that t
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ),
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t
7. Maximum DDR1 frequency is 400 MHz
8. Per the JEDEC spec the DDR2 duty cycle at 600 MHz is the average low and high cycle time values that are
9. Per the JEDEC spec the DDR2 duty cycle at 400 and 533 MHz is the low and high cycle time values.
(reference)(state)
be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went
invalid (AX or DX). For example, t
goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, t
timing (DD) for the time t
output hold time.
timing (DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
modified through control of the DQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This
will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in
the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8641
Integrated Processor Reference Manual for a description and understanding of the timing modifications enabled by
use of these bits.
ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the
microprocessor.
the symbol conventions described in note 1.
defined as the average pulse widths calculated across any consecutive 200 pulses. Jitter can sometimes force
single low and high cycle times to drift from the average values. t
DDKHMH
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
For the ADDR/CMD setup and hold specifications in
assumed that the Clock Control register is set to adjust the memory clocks
by 1/2 applied cycle.
Parameter
for inputs and t
Table 21. DDR SDRAM Output AC Timing Specifications (continued)
follows the symbol conventions described in note 1. For example, t
MCK
(first two letters of functional block)(reference)(state)(signal)(state)
memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data
DDKHAS
symbolizes DDR timing (DD) for the time t
Symbol
t
DDKHME
NOTE
1
(first two letters of functional block)(signal)(state)
JIT
–0.6
Min
= ±125 ps.
Table
for outputs. Output hold time can
MCK
21, it is
DDKHMH
Max
DDKLDX
0.6
memory clock reference (K)
symbolizes DDR
describes the DDR
Freescale Semiconductor
DDKHMH
DDKHMP
Unit
ns
can be
follows
Notes
6