MC8641DVU1333JE Freescale Semiconductor, MC8641DVU1333JE Datasheet - Page 76

• Manufacturer Part Number: MC8641DVU1333JE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8641DVU1333JE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.333GHz
• Voltage: 1.05V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Family Name: MPC8xxx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 1.333GHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.05V
• Operating Supply Voltage (max): 1.1V
• Operating Supply Voltage (min): 1V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1023
• Package Type: FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

PCI Express
provide additional margin to adequately compensate for the degraded minimum Receiver eye diagram
(shown in
simulations and the Return Loss measured looking into the RX package and silicon. The RX eye diagram
must be aligned in time using the jitter median to locate the center of the eye diagram.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX
UI.
14.5.1
The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2
inches of the package pins, into a test/measurement load shown in
76
Figure
Compliance Test and Measurement Load
Figure 51. Minimum Receiver Eye Timing and Voltage Compliance Specification
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
The reference impedance for return loss measurements is 50
both the D+ and D- line (that is, as measured by a Vector Network Analyzer
with 50
optional for the return loss measurement.
The allowance of the measurement point to be within 0.2 inches of the
package pins is meant to acknowledge that package/board routing may
benefit from D+ and D– not being exactly matched in length at the package
pin boundary.
51) expected at the input Receiver based on some adequate combination of system
Ω
probes—see
Figure
52). Note that the series capacitors, C
NOTE
NOTE
Figure
52.
Ω
to ground for
TX
Freescale Semiconductor
, are