MC8641DVU1333JE Freescale Semiconductor, MC8641DVU1333JE Datasheet - Page 13

• Manufacturer Part Number: MC8641DVU1333JE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8641DVU1333JE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.333GHz
• Voltage: 1.05V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Family Name: MPC8xxx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 1.333GHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.05V
• Operating Supply Voltage (max): 1.1V
• Operating Supply Voltage (min): 1V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1023
• Package Type: FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Figure 3
Freescale Semiconductor
Notes:
1. Dotted waveforms correspond to optional supply values for a specified power supply. See
2. The recommended maximum ramp up time for power supplies is 20 milliseconds.
3. Refer to
4. Refer to
5. e600 PLL relock time is 100 microseconds maximum plus 255 MPX_clk cycles.
6. Stable PLL configuration signals are required as stable SYSCLK is applied. All other POR configuration
7. V
8. SYSCLK must be driven only AFTER the power for the various power supplies is stable.
9. In device sleep mode, the reset configuration signals for DRAM types (TSEC2_TXD[4],TSEC2_TX_ER)
illustrates the Power Up sequence as described above.
assertion timing requirements.
addition see
inputs are required 4 SYSCLK cycles before HRESET negation and are valid at least 2 SYSCLK cycles
after HRESET has negated (hold requirement). See
information on setup and hold time of reset configuration signals.
D n _GV
must be valid BEFORE HRESET is asserted.
DD
3.3 V
2.5 V
1.8 V
1.2 V
_PLAT, AV
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
DD
0
Section 5, “RESET
Table 11
, and D n _MV
Configuration Pins
Figure 68
DD
for additional information on reset configuration pin setup timing requirements. In
_PLAT must strictly reach 90% of their recommended voltage before the rail for
Power Supply Ramp Up
Figure 3. MPC8641 Power-Up and Reset Sequence
7
regarding HRESET and JTAG connection details including TRST.
REF
Reset
SYSCLK
reaches 10% of their recommended voltage.
Initialization” for additional information on PLL relock and reset signal
L/TV
If
8 (not drawn to scale)
DD
=2.5 V
2
1
9
Section 5, “RESET
Cycles Setup and hold Time
SYSCLK is functional
100 µs Platform PLL
D n _MV
HRESET (& TRST)
D n _GV
Relock Time
Asserted for
100 μs after
DD
REF
V
AV
AV
V
L/T/OV
DD
DD
, = 1.8/2.5 V
DD
DD
Initialization” for more
_PLAT, AV
_Core n , AV
_LB, SV
_SRDS n
3
DD
4
DD
, XV
DD
6
DD
_PLAT
_Core n
DD
Table
Electrical Characteristics
e600
_SRDS n
PLL
5
2.
Time
13