LUPXA255A0C200

Manufacturer Part NumberLUPXA255A0C200
DescriptionIC MICRO PROCESSOR 200MHZ 256BGA
ManufacturerIntel
LUPXA255A0C200 datasheets
 


Specifications of LUPXA255A0C200

Processor TypeXScale®Speed200MHz
Voltage3.3VMounting TypeSurface Mount
Package / Case256-BGALead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names866868
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Package Information
Table 3.
Pin and Signal Descriptions for the PXA255 Processor (Sheet 2 of 9)
Pin Name
Type
SDRAM and/or Synchronous Static Memory clock
enable. (output) Connect to the clock enable pins of
SDCKE[1]
OC
SDRAM. It is deasserted during sleep. SDCKE[1] is
always de-asserted upon reset. The memory controller
provides control register bits for de-assertion.
Synchronous Static Memory clock. (output) Connect to
the clock (CLK) pins of SMROM. It is driven by either the
internal memory controller clock, or the internal memory
controller clock divided by 2. At reset, all clock pins are
free running at the divide-by-2 clock speed and may be
SDCLK[0]
OC
turned off via free-running control register bits in the
memory controller. The memory controller also provides
control register bits for clock division and deassertion of
each SDCLK pin. SDCLK[0] control register assertion bit
defaults to on if the boot-time static memory bank 0 is
configured for SMROM.
SDCLK[1]
OCZ
SDRAM Clocks (output) Connect SDCLK[1] and
SDCLK[2] to the clock pins of SDRAM in bank pairs 0/1
and 2/3, respectively. They are driven by either the
internal memory controller clock, or the internal memory
controller clock divided by 2. At reset, all clock pins are
free running at the divide-by-2 clock speed and may be
SDCLK[2]
OC
turned off via free-running control register bits in the
memory controller. The memory controller also provides
control register bits for clock division and de-assertion of
each SDCLK pin. SDCLK[2:1] control register assertion
bits are always de-asserted upon reset.
nCS[5]/
ICOCZ
GPIO[33]
nCS[4]/
ICOCZ
GPIO[80]
Static chip selects. (output) Chip selects to static
nCS[3]/
memory devices such as ROM and Flash. Individually
ICOCZ
programmable in the memory configuration registers.
GPIO[79]
nCS[5:0] can be used with variable latency I/O devices.
nCS[2]/
ICOCZ
GPIO[78]
nCS[1]/
ICOCZ
GPIO[15]
Static chip select 0. (output) Chip select for the boot
nCS[0]
ICOCZ
memory. nCS[0] is a dedicated pin.
Read/Write for static interface. (output) Signals that the
RD/nWR
OCZ
current transaction is a read or write.
Variable latency I/O ready pin. (input) Notifies the
RDY/
ICOCZ
memory controller when an external bus device is ready
GPIO[18]
to transfer data.
LCD display data. (output) Transfers pixel information
from the LCD controller to the external LCD panel.
L_DD[8]/
ICOCZ
Memory controller alternate bus master request.
GPIO[66]
(input) Allows an external device to request the system
bus from the memory controller.
10
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
Signal Descriptions
Reset State
Sleep State
Driven low
Driven low
Driven Low
Driven Low
Driven Low
Driven Low
Pulled High -
Note [4]
Note[1]
Driven High
Note [4]
Driven Low
Holds last state
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]