LUPXA255A0C200

Manufacturer Part NumberLUPXA255A0C200
DescriptionIC MICRO PROCESSOR 200MHZ 256BGA
ManufacturerIntel
LUPXA255A0C200 datasheets
 


Specifications of LUPXA255A0C200

Processor TypeXScale®Speed200MHz
Voltage3.3VMounting TypeSurface Mount
Package / Case256-BGALead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names866868
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Package Information
Table 3.
Pin and Signal Descriptions for the PXA255 Processor (Sheet 8 of 9)
Pin Name
Type
TEXTAL
IA
32 kHz crystal output. No external caps are required.
LCD display data. (output) Transfers pixel information
L_DD[12]/
from the LCD controller to the external LCD panel.
ICOCZ
GPIO[70]
RTC clock. (output) Real time clock 1 Hz tick.
LCD display data. (output) Transfers the pixel
information from the LCD controller to the external LCD
L_DD[13]/
panel.
ICOCZ
GPIO[71]
3.6864 MHz clock. (output) Output from 3.6864 MHz
oscillator.
LCD display data. (output) Transfers pixel information
L_DD[14]/
from the LCD controller to the external LCD panel.
ICOCZ
GPIO[72]
32 kHz clock. (output) Output from the 32 kHz oscillator.
48 MHz clock. (output) Peripheral clock output derived
from the PLL.
48MHz/GP[7]
ICOCZ
NOTE: This clock is only generated when the USB unit
clock enable is set.
RTCCLK/
Real time clock. (output) 1 Hz output derived from the
ICOCZ
GP[10]
32 kHz or 3.6864 MHz output.
3.6864 MHz clock. (output) Output from 3.6864 MHz
3.6MHz/GP[11]
ICOCZ
oscillator.
32kHz/GP[12]
ICOCZ
32 kHz clock. (output) Output from the 32 kHz oscillator.
Miscellaneous Pins
BOOT_SEL
IC
Boot select pins. (input) Indicates type of boot device.
[2:0]
Power Enable for the power supply. (output) When
PWR_EN
OC
negated, it signals the power supply to remove power to
the core because the system is entering sleep mode.
Main Battery Fault. (input) Signals that main battery is
low or removed. Assertion causes PXA255 processor
processor to enter sleep mode or force an imprecise data
nBATT_FAULT
IC
exception, which cannot be masked. PXA255 processor
will not recognize a wake-up event while this signal is
asserted. Minimum assertion time for nBATT_FAULT is 1
ms.
VDD Fault. (input) Signals that the main power source is
going out of regulation. nVDD_FAULT causes the
PXA255 processor to enter sleep mode or force an
nVDD_FAULT
IC
imprecise data exception, which cannot be masked.
nVDD_FAULT is ignored after a wake-up event until the
power supply timer completes (approximately 10 ms).
Minimum assertion time for nVDD_FAULT is 1 ms.
Hard reset. (input) Level -sensitive input used to start the
processor from a known address. Assertion terminates
the current instruction abnormally and causes a reset.
nRESET
IC
When nRESET is driven high, the processor starts
execution from address 0. nRESET must remain low until
the power supply is stable and the internal 3.6864 MHz
oscillator has stabilized.
16
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
Signal Descriptions
Reset State
Sleep State
Note [2]
Note [2]
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
Input
Input
Driven low while
entering sleep
Driven High
mode. Driven high
when sleep exit
sequence begins.
Input
Input
Input
Input
Input. Driving low
during sleep will
cause normal
Input
reset sequence
and exit from sleep
mode.