LUPXA255A0C200

Manufacturer Part NumberLUPXA255A0C200
DescriptionIC MICRO PROCESSOR 200MHZ 256BGA
ManufacturerIntel
LUPXA255A0C200 datasheets
 


Specifications of LUPXA255A0C200

Processor TypeXScale®Speed200MHz
Voltage3.3VMounting TypeSurface Mount
Package / Case256-BGALead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names866868
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Figure 5. GPIO Reset Timing
GP[1]
nRESET_OUT
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is
deasserted or the application processor will enter Sleep Mode
Table 17. GPIO Reset Timing Specifications
Symbol
Minimum assert time of GP[1]
tA_GP[1]
3.6864MHz input clock cycles
Delay between GP[1] asserted and
tDHW_OUT_A
nRESET_OUT asserted in 3.6864 MHz
input clock cycles
Delay between nRESET_OUT asserted
tDHW_OUT
and nRESET_OUT de-asserted, run or
turbo mode
Delay between nRESET_OUT asserted
tDHW_OUT_F
and nRESET_OUT de-asserted, during
frequency change sequence
Delay between nReset_Out de-asserted
tDHW_NCS0
and nCS0 asserted
NOTES:
1. GP[1] is not recognized as a reset source again until configured to do so in software. Software should
check the state of GP[1] before configuring as a reset to ensure no spurious reset is generated.
2. Time is 512*N processor clock cycles plus up to 4 cycles of the 3.6864-MHz input clock.
3. Time during the frequency change sequence depends on the state of the PLL lock detector at the
assertion of GPIO reset. The lock detector has a maximum time of 350µs plus synchronization.
4.7.5
Sleep Mode Timing
Sleep mode is asserted internally; and asserts the nRESET_OUT and PWR_EN signals. The
sequence indicated in
Mode Timing Specifications” on page 34
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
t
A_GP[1]
t
DHW_OUT_A
Description
1
in
2
3
150.69
Figure 6, “Sleep Mode Timing” on page 34
is the required timing parameters for sleep mode.
Electrical Specifications
t
DHW_OUT
Min
Typical
Max
Units
4
cycles
3
8
cycles
1.28
6.5
µs
µs
1.28
360
390
ns
and detailed in
Figure 18, “Sleep
33