LUPXA255A0C200

Manufacturer Part NumberLUPXA255A0C200
DescriptionIC MICRO PROCESSOR 200MHZ 256BGA
ManufacturerIntel
LUPXA255A0C200 datasheets
 


Specifications of LUPXA255A0C200

Processor TypeXScale®Speed200MHz
Voltage3.3VMounting TypeSurface Mount
Package / Case256-BGALead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names866868
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Table 3.
Pin and Signal Descriptions for the PXA255 Processor (Sheet 9 of 9)
Pin Name
Type
Reset out. (output) Asserted when nRESET is asserted
and deasserts after nRESET is de-asserted but before
nRESET_OUT
OC
the first instruction fetch. nRESET_OUT is also asserted
for “soft” reset events: sleep, watchdog reset, or GPIO
reset.
JTAG and Test Pins
JTAG test interface reset. Resets the JTAG/debug port.
If JTAG/debug is used, drive nTRST from low to high
nTRST
IC
either before or at the same time as nRESET. If JTAG is
not used, nTRST must be either tied to nRESET or tied
low.
JTAG test data input. (input) Data from the JTAG
TDI
IC
controller is sent to the PXA255 processor using this pin.
This pin has an internal pull-up resistor.
JTAG test data output. (output) Data from the PXA255
TDO
OCZ
processor is returned to the JTAG controller using this
pin.
JTAG test mode select. (input) Selects the test mode
TMS
IC
required from the JTAG controller. This pin has an
internal pull-up resistor.
JTAG test clock. (input) Clock for all transfers on the
TCK
IC
JTAG test interface.
TEST
IC
Test Mode. (input) Reserved. Must be grounded.
TESTCLK
IC
Test Clock. (input) Reserved. Must be grounded.
Power and Ground Pins
Positive supply for internal logic. Must be connected
VCC
SUP
to the low voltage supply on the PCB.
Ground supply for internal logic. Must be connected to
VSS
SUP
the common ground plane on the PCB.
Positive supply for PLLs and oscillators. Must be
PLL_VCC
SUP
connected to the common low voltage supply.
Ground supply for the PLL. Must be connected to
PLL_VSS
SUP
common ground plane on the PCB.
Positive supply for all CMOS I/O except memory bus
VCCQ
SUP
and PCMCIA pins. Must be connected to the common
3.3v supply on the PCB.
Ground supply for all CMOS I/O except memory bus
VSSQ
SUP
and PCMCIA pins. Must be connected to the common
ground plane on the PCB.
Positive supply for memory bus and PCMCIA pins.
VCCN
SUP
Must be connected to the common 3.3v or 2.5v supply on
the PCB.
Ground supply for memory bus and PCMCIA pins.
VSSN
SUP
Must be connected to the common ground plane on the
PCB.
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
Signal Descriptions
Package Information
Reset State
Sleep State
Driven low during
any reset sequence
Driven Low
- driven high prior to
first fetch.
Input
Input
Input
Input
Hi-Z
Hi-Z
Input
Input
Input
Input
Input
Input
Input
Input
Powered
Note [6]
Grounded
Grounded
Powered
Note [6]
Grounded
Grounded
Powered
Note [7]
Grounded
Grounded
Powered
Note [7]
Grounded
Grounded
17