LUPXA255A0C200

Manufacturer Part NumberLUPXA255A0C200
DescriptionIC MICRO PROCESSOR 200MHZ 256BGA
ManufacturerIntel
LUPXA255A0C200 datasheets
 


Specifications of LUPXA255A0C200

Processor TypeXScale®Speed200MHz
Voltage3.3VMounting TypeSurface Mount
Package / Case256-BGALead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names866868
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Table 4.
Pin Description Notes
Note
GPIO reset operation: Configured as GPIO inputs by default after any reset. The input buffers for these pins are
disabled to prevent current drain and the pins are pulled high with 10K to 60K internal resistors. The input paths
must be enabled and the pullups turned off by clearing the read-disable-hold (RDH) bit described in
[1]
Section 3.5.7, “Power Manager Sleep Status Register (PSSR)” on page 3-27 in the Intel® PXA255 Processor
Developers Manual. Even though sleep mode sets the RDH bit, the pull-up resistors are not re-enabled by sleep
mode.
Crystal oscillator pins: These pins connect the external crystals to the on-chip oscillators. Refer to Section 3.3.1,
“32.768 kHz Oscillator” on page 3-4 in the Intel® PXA255 Processor Developers Manual and Section 3.3.2,
[2]
“3.6864 MHz Oscillator” on page 3-4 of the Intel® PXA255 Processor Developers Manual for details on sleep-
mode operation.
GPIO sleep operation: The state of these pins is determined by the corresponding PGSRn during the transition
into sleep mode. See Section 3.5.9, “Power Manager GPIO Sleep State Registers (PGSR0, PGSR1, PGSR2)”
and Section 4.1.3.2, “GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)” on page 4-8 in the Intel®
PXA255 Processor Developers Manual. If selected as an input, this pin does not drive during sleep. If selected
[3]
as an output, the value contained in the sleep-state register is driven out onto the pin and held there while the
PXA255 processor is in sleep mode.
GPIOs configured as inputs after exiting sleep mode cannot be used until PSSR[RDH] is cleared.
Static memory control pins: During sleep mode, these pins can be programmed to either drive the value in the
sleep-state register or be placed in Hi-Z. To select the Hi-Z state, software must set the FS bit in the power-
[4]
manager general-configuration register. If PCFR[FS] is not set, then during the transition to sleep these pins
function as described in [3], above. For nWE, nOE, and nCS[0], if PCFR[FS] is not set, they are driven high by
the memory controller before entering sleep. If PCFR[FS] is set, these pins are placed in Hi-Z.
PCMCIA control pins: During sleep mode: can be programmed either to drive the value in the sleep-state
[5]
register or be placed in Hi-Z. To select the Hi-Z state, software must set PCFR[FP]. If it is not set, then during the
transition to sleep these pins function as described in [3], above.
[6]
During sleep, this supply may be driven low. This supply must never be high impedance.
[7]
Remains powered in sleep mode.
18
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
Description