LUPXA255A0C200

Manufacturer Part NumberLUPXA255A0C200
DescriptionIC MICRO PROCESSOR 200MHZ 256BGA
ManufacturerIntel
LUPXA255A0C200 datasheets
 


Specifications of LUPXA255A0C200

Processor TypeXScale®Speed200MHz
Voltage3.3VMounting TypeSurface Mount
Package / Case256-BGALead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names866868
1
2
3
4
5
6
7
8
9
10
11
Page 11
12
Page 12
13
Page 13
14
Page 14
15
Page 15
16
Page 16
17
Page 17
18
Page 18
19
Page 19
20
Page 20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Page 11/40

Download datasheet (2Mb)Embed
PrevNext
Table 3.
Pin and Signal Descriptions for the PXA255 Processor (Sheet 3 of 9)
Pin Name
Type
LCD display data. (output) Transfers pixel information
L_DD[15]/
from the LCD controller to the external LCD panel.
ICOCZ
GPIO[73]
Memory controller grant. (output) Notifies an external
device that it has been granted the system bus.
MBGNT/
Memory controller grant. (output) Notifies an external
ICOCZ
GP[13]
device that it has been granted the system bus.
Memory controller alternate bus master request.
MBREQ/
ICOCZ
(input) Allows an external device to request the system
GP[14]
bus from the memory controller.
PCMCIA/CF Control Pins
nPOE/
PCMCIA output enable. (output) Reads from PCMCIA
ICOCZ
memory and to PCMCIA attribute space.
GPIO[48]
PCMCIA write enable. (output) Performs writes to
nPWE/
ICOCZ
PCMCIA memory and to PCMCIA attribute space. Also
GPIO[49]
used as the write enable signal for variable latency I/O.
nPIOW/
PCMCIA I/O write. (output) Performs write transactions
ICOCZ
to PCMCIA I/O space.
GPIO[51]
nPIOR/
PCMCIA I/O read. (output) Performs read transactions
ICOCZ
from PCMCIA I/O space.
GPIO[50]
PCMCIA card enable 2. (output) Selects a PCMCIA
nPCE[2]/
card. nPCE[2] enables the high byte lane and nPCE[1]
ICOCZ
enables the low byte lane.
GPIO[53]
MMC clock. (output) Clock signal for the MMC controller.
PCMCIA card enable 1. (outputs) Selects a PCMCIA
nPCE[1]/
ICOCZ
card. nPCE[2] enables the high byte lane and nPCE[1]
GPIO[52]
enables the low byte lane.
IO Select 16. (input) Acknowledge from the PCMCIA
nIOIS16/
ICOCZ
card that the current address is a valid 16 bit wide I/O
GPIO[57]
address.
PCMCIA wait. (input) Driven low by the PCMCIA card to
nPWAIT/
ICOCZ
extend the length of the transfers to/from the PXA255
GPIO[56]
processor processor.
PCMCIA socket select. (output) Used by external
steering logic to route control, address, and data signals
PSKTSEL/
to one of the two PCMCIA sockets. When PSKTSEL is
ICOCZ
low, socket zero is selected. When PSKTSEL is high,
GPIO[54]
socket one is selected. Has the same timing as the
address bus.
PCMCIA register select. (output) Indicates that the
nPREG/
ICOCZ
target address on a memory transaction is attribute
GPIO[55]
space. Has the same timing as the address bus.
LCD Controller Pins
L_DD(7:0)/
LCD display data. (outputs) Transfers pixel information
ICOCZ
from the LCD Controller to the external LCD panel.
GPIO[65:58]
LCD display data. (output) Transfers pixel information
from the LCD controller to the external LCD panel.
L_DD[8]/
ICOCZ
Memory controller alternate bus master request.
GPIO[66]
(input) Allows an external device to request the system
bus from the Memory Controller.
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
Signal Descriptions
Package Information
Reset State
Sleep State
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
11