LUPXA255A0C200

Manufacturer Part NumberLUPXA255A0C200
DescriptionIC MICRO PROCESSOR 200MHZ 256BGA
ManufacturerIntel
LUPXA255A0C200 datasheets
 


Specifications of LUPXA255A0C200

Processor TypeXScale®Speed200MHz
Voltage3.3VMounting TypeSurface Mount
Package / Case256-BGALead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names866868
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Table 3.
Pin and Signal Descriptions for the PXA255 Processor (Sheet 7 of 9)
Pin Name
Type
2
AC97 Controller and I
S Controller Pins
AC97 audio port bit clock. (input) AC97 clock is
generated by Codec 0 and fed into the PXA255
processor processor and Codec 1.
AC97 Aaudio port bit clock. (output) AC97 clock is
BITCLK/
generated by the PXA255 processor.
ICOCZ
GPIO[28]
2
I
S bit clock. (input) I
and fed into PXA255 processor.
2
I
S bit clock. (output) I
PXA255 processor.
SDATA_IN0/
AC97 audio port data in. (input) Input line for Codec 0.
ICOCZ
2
GPIO[29]
I
S data in. (input) Input line for the I
AC97 audio port data in. (input) Input line for Codec 1.
SDATA_IN1/
ICOCZ
2
I
S system clock. (output) System clock from I
GPIO[32]
controller.
AC97 audio port data out. (output) Output from the
SDATA_OUT/
PXA255 processor to Codecs 0 and 1.
ICOCZ
GPIO[30]
2
I
S data out. (output) Output line for the I
AC97 audio port sync signal. (output) Frame sync
SYNC/
signal for the AC97 controller.
ICOCZ
2
GPIO[31]
I
S sync. (output) Frame sync signal for the I
controller.
nACRESET
OC
AC97 audio port reset signal. (output)
2
I
C Controller Pins
2
SCL
ICOCZ
I
C clock. (bidirectional)
2
SDA
ICOCZ
I
C data. (bidirectional).
PWM Pins
PWM[1:0]/
ICOCZ
Pulse width modulation channels 0 and 1. (outputs)
GPIO[17:16]
DMA Pins
DMA request. (input) Notifies the DMA Controller that an
DREQ[1:0]/
ICOCZ
external device requires a DMA transaction. DREQ[1] is
GPIO[19:20]
GPIO[19]. DREQ[0] is GPIO[20].
GPIO Pins
General purpose I/O. Wakeup sources on both rising
GPIO[1:0]
ICOCZ
and falling edges on nRESET.
General purpose I/O. More wakeup sources for sleep
GPIO[14:2]
ICOCZ
mode.
General purpose I/O. Additional General Purpose I/O
GPIO[22:21]
ICOCZ
pins.
Crystal and Clock Pins
3.6864 MHz crystal input. No external caps are
PXTAL
OA
required.
3.6864 MHz crystal output. No external caps are
PEXTAL
IA
required.
TXTAL
OA
32 KHz crystal input. No external caps are required.
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
Signal Descriptions
2
S clock is generated externally
2
S clock is generated by the
2
S controller.
2
S
2
S controller.
2
S
Package Information
Reset State
Sleep State
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
Driven Low
Driven Low
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
Note [2]
Note [2]
Note [2]
Note [2]
Note [2]
Note [2]
15