LUPXA255A0C200

Manufacturer Part NumberLUPXA255A0C200
DescriptionIC MICRO PROCESSOR 200MHZ 256BGA
ManufacturerIntel
LUPXA255A0C200 datasheets
 


Specifications of LUPXA255A0C200

Processor TypeXScale®Speed200MHz
Voltage3.3VMounting TypeSurface Mount
Package / Case256-BGALead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names866868
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Page 31
32
Page 32
33
Page 33
34
Page 34
35
Page 35
36
Page 36
37
Page 37
38
Page 38
39
Page 39
40
Page 40
Page 36/40

Download datasheet (2Mb)Embed
PrevNext
Electrical Specifications
Table 21. Card Interface (PCMCIA or Compact Flash) AC Specifications
Symbol
MA(25:0), nPREG, PSKTSEL, nPCE setup to nPWE, nPOE, nPIOW, or
tcardAS
nPIOR asserted
MA(25:0), nPREG, PSKTSEL, nPCE hold after nPWE, nPOE, nPIOW, or
tcardAH
nPIOR de-asserted
tcardDS
MD(31:0) setup to nPWE, nPOE, nPIOW, or nPIOR asserted
tcardDH
MD(31:0) hold after nPWE, nPOE, nPIOW, or nPIOR de-asserted
tcardCMD
nPWE, nPOE, nPIOW, or nPIOR command assertion
NOTE: These numbers are minimums. They can be much longer based on the programmable card
interface timing registers.
Table 22. Synchronous Memory Interface AC Specifications
Symbol
SDRAM / SMROM / SDRAM-Timing Synchronous Flash (Synchronous)
tsynCLK
SDCLK period
tsynCMD
nSDCAS, nSDRAS, nWE, nSDCS assert time
tsynRCD
nSDRAS to nSDCAS assert time
tsynCAS
nSDCAS to nSDCAS assert time
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS,
tsynSDOS
nWE, nOE, SDCKE(1:0), RDnWR output setup time to SDCLK(2:0)
rise
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS,
tsynSDOH
nWE, nOE, SDCKE(1:0), RDnWR output hold time from
SDCLK(2:0) rise
tsynSDIS
MD(31:0) read data input setup time from SDCLK(2:0) rise
tsynDIH
MD(31:0) read data input hold time from SDCLK(2:0) rise
Fast Flash (Synchronous READS only)
tffCLK
SDCLK period
tffAS
MA(25:0) setup to nSDCAS (as nADV) asserted
tffCES
nCS setup to nSDCAS (as nADV) asserted
tffADV
nSDCAS (as nADV) pulse width
tffOS
nSDCAS (as nADV) de-assertion to nOE assertion
tffCEH
nOE deassertion to nCS de-assertion
NOTES:
1. These numbers are for a maximum 99.5 MHz MEMCLK and 99.5 MHz output SDCLK.
2. SDCLK for SDRAM, SMROM, and SDRAM-timing Synchronous Flash can be at the slowest, divide-by-2 of
the 99.5 MHz MEMCLK. It can be 99.5 MHz at the fastest.
3. This number represents 1/2 SDCLK period.
4. SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of
the 132.7 MHz MEMCLK at its fastest.
36
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
Description
1
Description
MEMCLKs
2
2
2
2
2
Units,
MIN
MAX
Notes
10
20
ns, 2
1
sdclk
1
sdclk
2
sdclk
3.8
ns, 3
3.6
ns, 3
0.5
ns
1.5
ns
15
20
ns, 4
0.5
sdclk
0.5
sdclk
1
sdclk
3
sdclk
4
sdclk