NHPXA270C5C520 Intel, NHPXA270C5C520 Datasheet - Page 66

• Manufacturer Part Number: NHPXA270C5C520
• Description: IC MPU 32BIT 520MHZ 356-PBGA
• Manufacturer: Intel

Specifications of NHPXA270C5C520

• Processor Type: XScale®
• Speed: 520MHz
• Voltage: 1.45V
• Mounting Type: Surface Mount
• Package / Case: 356-PBGA
• For Use With: 460-3472 - KIT DEV ZOOM STARTER FOR PXA270
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 868459

Intel® PXA270 Processor
AC Timing Specifications
6.2
6.2.1
6-2
Figure 6-1. AC Test Load
Reset and Power Manager Timing Specifications
The processor asserts the nRESET_OUT pin in one of several different modes:
The following sections give the timing and specifications for entry into and exit from these modes.
Power-On Timing Specifications
Power-on reset begins when a power supply is detected on the backup battery pin, VCC_BATT,
after the processor has been powered off. A power-on reset is equivalent to a hardware reset, in that
all units are reset to the same known state as with a hardware reset. A power-on reset is a complete
and total reset that occurs only at initial power on.
The external power-supply system must enable the power supplies for the processor in a specific
sequence to ensure proper operation.
sequence.
The sequence for power-on reset is as follows:
1. VCC_BATT is established, then nRESET should be de-asserted to initiate power-on reset.
2. PWR_OUT is asserted. The processor asserts nRESET_OUT.
3. The external power-control subsystem de-asserts nBATT_FAULT to signal that the main
4. The processor asserts the SYS_EN signal to enable the power supplies VCC_IO, VCC_MEM,
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•
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Power-on reset
Hardware reset
Watchdog reset
GPIO reset
Sleep mode
Deep-sleep mode
battery is connected and not discharged.
VCC_BB, VCC_USB, and VCC_LCD. VCC_USIM can be established at this time also but
can be independently controlled through its own control signals. VCC_IO must be established
first. The other supplies can turn on in any order, but they must all be established within
125 milliseconds of the assertion of SYS_EN.
Table 6-2
details the timing.
I/O
Figure 6-2
ΖΟ = 50Ω
Electrical, Mechanical, and Thermal Specification
shows the timing diagram for a power-on reset
50pf