NHPXA270C5C520 Intel, NHPXA270C5C520 Datasheet - Page 78

• Manufacturer Part Number: NHPXA270C5C520
• Description: IC MPU 32BIT 520MHZ 356-PBGA
• Manufacturer: Intel

Specifications of NHPXA270C5C520

• Processor Type: XScale®
• Speed: 520MHz
• Voltage: 1.45V
• Mounting Type: Surface Mount
• Package / Case: 356-PBGA
• For Use With: 460-3472 - KIT DEV ZOOM STARTER FOR PXA270
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 868459

Symbols
tsdSDIS
tsdSDIH
NOTES:
1. SDCLK for SDRAM slowest period is accomplished by divide-by-2 of the 26-MHz CLK_MEM. The fastest possible SDCLK is
2. SDCLK1 and SDCLK2 frequencies are configured to be CLK_MEM frequency divided by 1 or 2, depending on the bit fields
3. These numbers are for VCC_MEM = 1.8 V +20% / –5%, VOL = 0.4 V, and VOH = 1.4 V, with each applicable 4-bit field of the
4. These numbers are for VCC_MEM = 2.5 V +/– 10%, VOL = 0.4 V, and VOH = 2.1 V, with each applicable 4-bit field of the system
5. These numbers are for VCC_MEM = 3.3 V +/– 10%, VOL = 0.4 V, and VOH = 2.4 V, with each applicable 4-bit field of the system
6. Refer to the “Memory Controller” chapter in the Intel® PXA27x Processor Family Developer’s Manual for register configuration.
Intel® PXA270 Processor
AC Timing Specifications
6-14
accomplished by configuring CLK_MEM at 104 MHz and not setting MDREFR[KxDB2].
MDREFR[K1DB2] and MDREFR[K2DB2] settings.
system memory buffer strength registers (BSCNTRP and BSCNTRN) set to TBD (msb:lsb) and each applicable SDCLK<2:1>
divide-by-2 and divide-by-4 register bits MDREFR[KxDB2] clear.
memory buffer strength registers (BSCNTRP and BSCNTRN) set to 0b1010 (msb:lsb) and each applicable SDCLK<2:1> divide-
by-2 and divide-by-4 register bit MDREFR[KxDB2] clear.
memory buffer strength registers (BSCNTRP and BSCNTRN) set to 0b1010 (msb:lsb) and each applicable SDCLK<2:1> divide-
by-2 and divide-by-4 register bit MDREFR[KxDB2] clear.
Table 6-15. SDRAM Interface AC Specifications (Sheet 2 of 2)
Parameters
MD<31:0> read
data input setup
time from
SDCLK<2:1> rise
MD<31:0> read
data input hold
time from
SDCLK<2:1> rise
TBD
TBD
MIN
1.8V +20% / –5%
VCC_MEM =
TYP
—
—
MAX
3
—
—
MIN
0.5
1.8
2.5V +/- 10%
VCC_MEM =
Electrical, Mechanical, and Thermal Specification
TYP
—
—
4
MAX
—
—
MIN
0.5
1.8
3.3V +/- 10%
VCC_MEM =
TYP
—
—
5
MAX
—
—
Units
ns
ns
—
—