NHPXA270C5C520 Intel, NHPXA270C5C520 Datasheet - Page 93

• Manufacturer Part Number: NHPXA270C5C520
• Description: IC MPU 32BIT 520MHZ 356-PBGA
• Manufacturer: Intel

Specifications of NHPXA270C5C520

• Processor Type: XScale®
• Speed: 520MHz
• Voltage: 1.45V
• Mounting Type: Surface Mount
• Package / Case: 356-PBGA
• For Use With: 460-3472 - KIT DEV ZOOM STARTER FOR PXA270
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 868459

Electrical, Mechanical, and Thermal Specification
Note: All AC timings must be considered to avoid timing violations in the memory-to-memory-controller
The burst read example shown in
SXCNFG[SXCLx] is configured as 0b0100, representing a frequency configuration code equal to
3. The following example can be used to help determine the appropriate setting for
SXCNFG[SXCLx].
Parameters defined by the processor:
Parameters defined by flash memory:
Use the following equations when calculating the frequency configuration code:
Example
The timing information below is only an example. See
timings.
Use equation 4 to help verify the maximum possible frequency at which the synchronous flash
memory can run with the memory controller. The following example uses equation 4:
The results from this example indicate that the 66-MHz memory works without problems with the
memory controller.
interface.
•
•
•
•
•
tffSDOH (max) = SDCLK<0> to CE# (nCE), ADV# (nADV), or address valid, whichever
occurs last
tffSDIS (min) = Data setup to SDCLK<0>
tVLQV (min) = ADV# low to output delay
tVLCH (min) = ADV# low to clock
tCHQV (max) = SDCLK<0> to output valid
(1) SDCLK period = (1 / frequency)
(2) n (SDCLK period)
(3) n = (tVLQV - tVLCH - tCHQV) / SDCLK period, where
(4) SDCLK period
SDCLK<0> frequency = 50 MHz
tVLQV = 70 ns (typical timing from synchronous flash memory)
tVLCH = 10 ns (min)
tCHQV = 14 ns (min)
From Eq.(1):
From Eq.(2):
SDCLK<0> frequency = 66 MHz
tCHQV = 11 ns (max)
tffSDIS = 3 ns (min)
From Eq. (1):
From Eq. (4):
n = frequency configuration code rounded up to integer value
≥
1 / 50 (MHz) = 20 ns
n(20 ns)
n(20 ns)
n = (46 / 20) ns = 2.3 ns
n = 3
1 / 66 (MHz) = 15.15 ns
15.15 ns
15.15 ns
tCHQV + tffSDIS
≥
tVLQV - tVLCH - tCHQV
Figure 6-18
≥
≥
≥
≥
70 ns - 10 ns - 14 ns
46 ns
11 ns + 3 ns
14 ns
represents waveforms that result when
Table 6-17
for actual synchronous AC
AC Timing Specifications
Intel® PXA270 Processor
6-29