NHPXA270C5C520 Intel, NHPXA270C5C520 Datasheet - Page 70

• Manufacturer Part Number: NHPXA270C5C520
• Description: IC MPU 32BIT 520MHZ 356-PBGA
• Manufacturer: Intel

Specifications of NHPXA270C5C520

• Processor Type: XScale®
• Speed: 520MHz
• Voltage: 1.45V
• Mounting Type: Surface Mount
• Package / Case: 356-PBGA
• For Use With: 460-3472 - KIT DEV ZOOM STARTER FOR PXA270
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 868459

Intel® PXA270 Processor
AC Timing Specifications
6.2.5
6-6
Table 6-5. GPIO Reset Timing Specifications
Note: When bit SL_ROD is set in the Power Manager Sleep Configuration register, nRESET_OUT, is
Sleep Mode Timing
Sleep mode is internally asserted, and it asserts the nRESET_OUT and PWR_EN signals.
Figure 6-5
not asserted during GPIO reset. See the “Clocks and Power Manager” chapter in the Intel®
PXA27x Processor Family Developer’s Manual for register details.
Symbol
tA_GPIO<1>
tDHW_OUT_A
tDHW_OUT
tDHW_OUT_F
tCS0
NOTES:
1. GPIO<1> is not recognized as a reset source again until configured to do so in software. Software must
2. Time is 512*N processor clock cycles plus up to 4 cycles of the 13.000-MHz input clock.
3. Time during the frequency-change sequence depends on the state of the PLL lock detector at the assertion
4. In standby, sleep, and deep-sleep modes, this time is in addition to the wake-up time from the low-power
5. The tCS0 specification is also applicable to Power-On reset, Hardware reset, Watchdog reset and Deep-
check the state of GPIO<1> before configuring as a reset to ensure that no spurious reset is generated. For
details, see the “Clocks and Power Manager” chapter in the Intel® PXA27x Processor Family Developer’s
Manual.
of GPIO reset. The lock detector has a maximum time of 350 µs plus synchronization.
mode.
Sleep/Sleep mode exit.
5
and
Table 6-6
Description
Minimum assert time of GPIO<1>
13.000-MHz input clock cycles
Delay between GPIO<1> asserted and
nRESET_OUT asserted in 13.000-MHz
input clock cycles
Delay between nRESET_OUT asserted
and nRESET_OUT de-asserted, run or
turbo mode
Delay between nRESET_OUT asserted
and nRESET_OUT de-asserted, during
frequency change sequence
Delay between nRESET_OUT de-
assertion and nCS0 assertion
show the required timing parameters for sleep mode.
2
3
Electrical, Mechanical, and Thermal Specification
1
in
1000
Min
230
4
6
5
4
4
Typical
—
—
—
—
—
Max
380
—
—
—
8
cycles
cycles
Units
nsec
µs
ns