NHPXA270C5C520 Intel, NHPXA270C5C520 Datasheet - Page 75

• Manufacturer Part Number: NHPXA270C5C520
• Description: IC MPU 32BIT 520MHZ 356-PBGA
• Manufacturer: Intel

Specifications of NHPXA270C5C520

• Processor Type: XScale®
• Speed: 520MHz
• Voltage: 1.45V
• Mounting Type: Surface Mount
• Package / Case: 356-PBGA
• For Use With: 460-3472 - KIT DEV ZOOM STARTER FOR PXA270
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 868459

6.2.10
6.3
Electrical, Mechanical, and Thermal Specification
Table 6-12. Voltage-Change Timing Specification for a 1-Byte Command
Table 6-13. GPIO Timing Specifications
Voltage-Change Timing
The PWR I
mode operation is supported). Software controls the time required for initiating the voltage change
sequence through completion. The voltage-change timing is a product of the number of commands
issued plus the number of software programmed delays.
command issued to the power manager IC.
Set the I
VCC_CORE ramp rate specification in the Electrical Section) to support VCC_CORE dynamic
voltage management.
GPIO Timing Specifications
Table 6-13
Symbol
NOTES:
Symbol
taGPIO
taGPIOLP
tdGPIO
tdGPIOLP
tdiGPIO
tdiGPIOLP
NOTES:
Note 4 describes the complete timing for a standby, sleep, or deep-sleep wake up source to be asserted and detected internally
1. Write 1 to PWRMODE[VC]
2. 40 kHz cycles
1. Period equal to two 13-MHz cycles
2. Period equal to two 32-kHz cycles
3. Period equal to three 13-MHz cycles
4. Period equal to three 32-kHz cycles
(2 cycles for assertion (note 2) and 1 additional cycle for detection).
—
1
1
3
2
C programmable output ramp rate with a default/reset ramp rate of 10mV/µs (refer to
2
2
4
shows the general-purpose I/O (GPIO) AC timing specifications.
2
C uses the regular I
Parameter
Assertion time required to detect
GPIO edge
Assertion time required to detect
GPIO low-power edge
De-assertion time required to
detect GPIO edge
De-assertion time required to
detect GPIO low-power edge
Time it takes for a GPIO edge to
be detected internally
Time it takes for a GPIO low-
power edge to be detected
internally
Description
Delay between voltage change sequence
start
1
to command received by PMIC
2
C protocol. The PWR I
93.75
62.5
62.5
Min
154
154
231
Max
—
—
—
—
—
—
2
Table 6-12
C is clocked at 40 kHz (160 kHz fast-
Min
—
Units
ns
µs
ns
µs
ns
µs
shows the timing of a 1 byte
Typical
Notes
run, idle, or sense power modes
standby, sleep, or deep-sleep
power modes
run, idle, or sense power modes
standby, sleep, or deep-sleep
power modes
run, idle, or sense power modes
standby, sleep, or deep-sleep
power modes
AC Timing Specifications
Intel® PXA270 Processor
18
Max
—
cycles
Units
6-11
2