NHPXA270C5C520 Intel, NHPXA270C5C520 Datasheet - Page 68

• Manufacturer Part Number: NHPXA270C5C520
• Description: IC MPU 32BIT 520MHZ 356-PBGA
• Manufacturer: Intel

Specifications of NHPXA270C5C520

• Processor Type: XScale®
• Speed: 520MHz
• Voltage: 1.45V
• Mounting Type: Surface Mount
• Package / Case: 356-PBGA
• For Use With: 460-3472 - KIT DEV ZOOM STARTER FOR PXA270
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 868459

Intel® PXA270 Processor
AC Timing Specifications
6.2.2
6-4
Table 6-2. Power-On Timing Specifications (Sheet 2 of 2)(OSCC[CRI] = 0)
Figure 6-3. Hardware Reset Timing
Table 6-3. Hardware Reset Timing Specifications (OSCC[CRI] = 0)
Hardware Reset Timing
The timing sequences shown in
and
indicated in
Symbol
t
t
NOTES:
NOTE: This long delay is attributed to the fact that when the CRI bit is read as 1, (which indicates that the
Symbol
t
t
t
sysramp
pwrramp
6
7
8
1. If the OSCC[CRI] =1 then the delay from nRESET de-assertion to SYS_EN assertion is 3000mS
Table 6-4
nRESET_OUT
CLK_REQ pin was floated during a hardware or power-on reset) the processor oscillator is supplied
externally. This then forces the system to wait for the 32 kHz oscillator and the 13 MHz oscillator to
stabilize.
nRESET
NOTE: nBATT_FAULT and nVDD_FAULT must be deasserted during the reset sequence.
Section 6.2.1
assume stable power supplies at the assertion of nRESET. Follow the timings
Description
Power-on Ramp Rate for all external high
-voltage power domains
Power-on Ramp Rate for all external low
-voltage power domains (including
dynamic voltage changes on
VCC_CORE)
Description
Delay between nRESET asserted and
nRESET_OUT asserted
Assertion time of nRESET
Delay between nRESET de-asserted and
nRESET_OUT de-asserted
if the power supplies are unstable.
Figure 6-3
t6
for hardware reset and the specifications in
Electrical, Mechanical, and Thermal Specification
t7
Min
—
—
Min
256
—
6
Typical
< 100 ns
Typical
10
10
—
—
t8
Max
12
12
Max
265
10
—
Table 6-3
mV/uS
mV/uS
Units
Units
ms
ms
ms