NHPXA270C5C520 Intel, NHPXA270C5C520 Datasheet - Page 71

• Manufacturer Part Number: NHPXA270C5C520
• Description: IC MPU 32BIT 520MHZ 356-PBGA
• Manufacturer: Intel

Specifications of NHPXA270C5C520

• Processor Type: XScale®
• Speed: 520MHz
• Voltage: 1.45V
• Mounting Type: Surface Mount
• Package / Case: 356-PBGA
• For Use With: 460-3472 - KIT DEV ZOOM STARTER FOR PXA270
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 868459

6.2.6
Electrical, Mechanical, and Thermal Specification
VCC_CORE, VCC_SRAM,
Figure 6-5. Sleep Mode Timing
Table 6-6. Sleep-Mode Timing Specifications
Intel® PXA27x State:
VCC_LCD, VCC_USIM
VCC_BB,VCC_MEM,
VCC_USB, VCC_IO,
Wakeup Event
nRESET_OUT
nVDD_FAULT
VCC_PLL
PWR_EN
SYS_EN
Deep-Sleep Mode Timing
Deep-sleep mode is internally asserted, and it asserts the nRESET_OUT and PWR_EN signals.
Figure 6-6
specifications listed are for software invoked (not battery or VDD fault) Deep-sleep entry, unless
specified.
Symbol
t
t
t
NOTES:
NOTE: 6ms is user programmable using the OSCC[OSD] bit. The remaining 5ms is an internal timer which
entry
exit
pwrdelay
1. -1mS if not using DC2DC and -0.94mS if any internal SRAM banks are not powered
2. 0.15ms less time if exiting from sleep mode to 13M mode
3. Add 0.1ms if the wake up event is external
4. Oscillator start/crystal stable times are programmable (300uS-11mS)
5. nRESET_OUT and nVDD_FAULT are programmable during sleep mode
5
(Enabled)
counts until the oscillator is stable. (Typical stabilization is 500µs. Maximum can be upto 5ms)
(High)
and
SLEEP (ENTRY)
Tentry
Table 6-7
Description
Delay between MCR sleep command
issue to de-assertion of PWR_EN
Delay between wakeup event and run
mode
Delay between assertion of PWR_EN to
PLL enable
2
show the required timing parameters for sleep mode. The timing
SLEEP
0.56
0.50
Min
0
SLEEP (EXIT)
Texit
Tpwrdelay
AC Timing Specifications
Typical
Intel® PXA270 Processor
—
—
—
136.65
Max
2.5
125
1
NORMAL
3
2,4
Units
msec
msec
msec
6-7