NHPXA270C5C520 Intel, NHPXA270C5C520 Datasheet - Page 73

• Manufacturer Part Number: NHPXA270C5C520
• Description: IC MPU 32BIT 520MHZ 356-PBGA
• Manufacturer: Intel

Specifications of NHPXA270C5C520

• Processor Type: XScale®
• Speed: 520MHz
• Voltage: 1.45V
• Mounting Type: Surface Mount
• Package / Case: 356-PBGA
• For Use With: 460-3472 - KIT DEV ZOOM STARTER FOR PXA270
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 868459

6.2.6.1
Electrical, Mechanical, and Thermal Specification
Table 6-8. GPIO Pu/Pd Timing Specifications for Deep-Sleep Mode
Note: GPIOs<0,1,3,4,9,10> never float. They are powered from VCC_BATT so when the system and the
Note: If the external high voltage power domains (VCC_IO, VCC_MEM, VCC_BB, VCC_LCD,
GPIO states in Deep-Sleep mode
If the external high voltage power domains (VCC_IO, VCC_MEM, VCC_BB, VCC_LCD,
VCC_USB, VCC_USIM) remain powered on during deep-sleep, the PGSR values are driven onto
all the GPIO pins (that are configured as outputs) for a finite time period, then the pins default to
the reset state (Pu/Pd) as described in Chapter 2 of this manual. This sequence occurs for either
software initiated or fault initiated deep-sleep entry.
core power domains are removed (controlled by SYS_EN and PWR_EN), the Pu/Pd resistors are
still enabled due to VCC_BATT remaining on.
The delay between the initiation of deep-sleep mode and enabling the GPIO Pu/Pd states, is system
dependant because the processor is performing an unpredictable workload and requires an
unknown amount of time to complete current processes. Refer to the deep-sleep mode, “Clocks and
Power” section of the Intel® PXA27x Processor Family Developers Manual for a description on
deep-sleep mode entry sequence.
Table 6-8
the regulators and converter naming conventions:
VCC_USB, VCC_USIM) are powered off during deep-sleep mode, the GPIOs behave the same as
described above; however, they float after the supplies are removed.
Description
Duration of the GPIO Pu/Pd states being
enabled and the de-assertion of
PWR_EN
L1 = Sleep/Deep-Sleep Linear Regulator
L2 = High-Current Linear Regulator
DC2DC = Sleep/Deep-Sleep DC-DC Converter
shows the time period that the GPIO pull-up/pull-downs are enabled. Listed below are
0.1
L2
0.13
L1
DC2DC
1.13
AC Timing Specifications
Intel® PXA270 Processor
Units
msec
6-9