NHPXA270C5C520 Intel, NHPXA270C5C520 Datasheet - Page 72

• Manufacturer Part Number: NHPXA270C5C520
• Description: IC MPU 32BIT 520MHZ 356-PBGA
• Manufacturer: Intel

Specifications of NHPXA270C5C520

• Processor Type: XScale®
• Speed: 520MHz
• Voltage: 1.45V
• Mounting Type: Surface Mount
• Package / Case: 356-PBGA
• For Use With: 460-3472 - KIT DEV ZOOM STARTER FOR PXA270
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 868459

Intel® PXA270 Processor
AC Timing Specifications
6-8
VCC_CORE, VCC_SRAM,
Intel® PXA27x State:
Figure 6-6. Deep-Sleep-Mode Timing
Table 6-7. Deep-Sleep Mode Timing Specifications
VCC_LCD, VCC_USIM
VCC_BB, VCC_MEM,
VCC_USB, VCC_IO,
nRESET_OUT
nVDD_FAULT
Wakeup Event
VCC_PLL
PWR_EN
SYS_EN
Deep-Sleep Command
Symbol
t
t
t
t
t
NOTE: Timing specifications for nBATT_FAULT and/or nVDD_FAULT asserted deep-sleep mode entry are
NOTES:
NOTE: 6ms is user programmable using the OSCC[OSD] bit. The remaining 5ms is an internal timer which
dentry
enable
dexit
dsysdelay
dpwrdelay
1. -1ms if not using DC2DC
2. 0.15ms less time if exiting from Deep-sleep mode to 13M mode
3. Add 0.1ms if the wake up event is external
4. Oscillator start/crystal stable times are programmable (300uS-11mS)
5. nRESET_OUT and nVDD_FAULT are programmable during sleep mode
6. Assumes PMCR[BIDAE or VIDAE] bits are set to zero (default state) - The PMCR[BIDAE or VIDAE] bits
Fault assert
are only read by the processor if nBATT_FAULT or nVDD_FAULT signals are asserted
5
DEEP SLEEP (ENTRY)
below:
counts until the oscillator is stable. (Typical stabilization is 500µs. Maximum can be upto 5ms)
Tdentry
Tenable
Description
Delay between deep-sleep command
issue to de-assertion of SYS_EN
Delay between de-assertion of PWR_EN
and SYS_EN
Delay between wakeup event and run
mode
Delay between assertion of SYS_EN to
PWR_EN
Delay between assertion of PWR_EN to
PLL enable
Delay between nBATT_FAULT or
nVDD_FAULT assertion (during all
modes of operation including sleep
mode) and deep-sleep mode entry
de-assertion of SYS_EN defines when
the processor is in deep-sleep mode)
2
2
DEEP SLEEP
Electrical, Mechanical, and Thermal Specification
6
(The
Tdsys_delay
0.66
0.60
0.33
Min
DEEP SLEEP (EXIT)
—
0
0
Tdexit
Tdpwr_delay
Typical
30
—
—
—
—
—
261.75
Max
1.66
1.56
125
125
—
NORMAL
3
1
2,4
Units
msec
msec
msec
msec
msec
usec