IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 117

• Manufacturer Part Number: IDT82V2108PX8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX8

IDT82V2108
4.1.3.4
CAS/RBS Buffer, the indirect registers of these blocks must be initialized
to eliminate erroneous control data. The PCCE (b0, E1-05CH & b0, E1-
060H & b0, E1-064H) of these blocks must be set to logic 1 to enable
these blocks.
be checked before a new access request to the RPLC, TPLC and RCRB
indirect registers. When the BUSY is logic 0, the new reading and writing
access operations can be performed.
RCRB indirect registers. Figure 78 shows the reading sequence of the
RPLC, TPLC and RCRB indirect registers.
Operation
Figure 77. Writing Sequence of Indirect Register in E1
Before using the Receive/Transmit Payload Control and Receive
Then the BUSY (b7, E1-05DH & b7, E1-061H & b7, E1-065H) must
Figure 77 shows the writing sequence of the RPLC, TPLC and
Using Payload Control and Receive CAS/RBS Buffer
RWB=0 and address is specified
in the Channel Indirect Address/
Y
Indirect Data Buffer Register
Data are set in the Channel
Control Register.
Set PCCE=1
to be written
Mode
More data
BUSY=0
End
Y
N
N
107
4.1.3.5
Control registers can be set as the follows:
- Transmit Clock Slave Mode (System Backplane Rate: 2.048 Mbit/s)
clock. TSCCKA and TSCCKB are both equal to 2.048 M. The N1 (b7~0,
E1-025H) and N2 (b7~0, E1-026H) are set to their default value (2FH).
- Transmit Clock Slave Mode (System Backplane Rate: 4.096 Mbit/s)
CKA is equal to 2.048 M. The N1 (b7~0, E1-025H) and N2 (b7~0, E1-
026H) are set to their default value (2FH).
- Transmit Clock Master Mode
Figure 78. Reading Sequence of Indirect Register in E1
In different operation modes, the Timing Options and Clock Divisor
TSCCKA or TSCCKB is selected as the TJAT DPLL input reference
The smoothed clock output from the TJAT is selected as LTCK.
TSCCKA is selected as the TJAT DPLL input reference clock. TSC-
The smoothed clock output from the TJAT is selected as LTCK.
XCK/24 is selected as the TJAT DPLL input reference clock.
XCK/24 is selected as LTCK.
Using TJAT / Timing Option
RWB=1 and address is specified in
Y
the Channel Indirect Address/
Read Channel Indirect Data
Mode
Control Register.
Buffer Register
Set PCCE=1
More data
to be read
BUSY=0
BUSY=0
T1 / E1 / J1 OCTAL FRAMER
End
Y
Y
N
N
N
March 5, 2009