IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 235

• Manufacturer Part Number: IDT82V2108PX8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX8

IDT82V2108
T1 / J1 ELSB Idle Code (01EH, 09EH, 11EH, 19EH, 21EH, 29EH, 31EH, 39EH)
be inserted.
register is written to when the framer is out of frame.
T1 / J1 FRMP Configuration (020H, 0A0H, 120H, 1A0H, 220H, 2A0H, 320H, 3A0H)
M20[1:0]:
ESFFA:
ESF synchronization is acquired. However, if there are mimic framing patterns in the received data stream, the ESF In-frame is not declared.
acquired. In this condition, the existence of the mimic framing patterns is not considered.
ESF:
JYEL:
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
These bits set the idle code that will replace the data on RSDn/MRSD automatically when it is out of SF/ESF synchronization. D7 is the first bit to
The writing of the idle code pattern is asynchronous with respect to the output data clock. One channel of idle code data will be corrupted if the
These bits select the SF/ESF frame loss criteria.
= 00: 2 of 4 frame alignment bits in error.
= 01: 2 of 5 frame alignment bits in error.
= 10: 2 of 6 frame alignment bits in error.
= 11: Reserved
This bit selects the framing algorithm for ESF format.
= 0: If four consecutive Frame Alignment Patterns are detected in the F-Bit in the received data stream without the mimic framing pattern, the
= 1: When 6 consecutive Frame Alignment Patterns are received error free and the CRC-6 checksum is also error free, the synchronization is
This bit selects the SF or ESF format in the Frame Processor block.
= 0: SF format is selected.
= 1: ESF format is selected.
This bit selects the T1 or J1 mode in the Frame Processor block.
= 0: T1 mode is selected.
= 1: J1 mode is selected.
M2O[1]
R/W
R/W
D7
7
1
7
0
M20[0]
R/W
R/W
D6
6
1
6
0
ESFFA
R/W
R/W
D5
5
1
5
0
R/W
ESF
R/W
D4
4
1
4
0
225
JYEL
R/W
R/W
D3
3
1
3
0
R/W
D2
2
1
2
T1 / E1 / J1 OCTAL FRAMER
Reserved
R/W
D1
1
1
1
March 5, 2009
R/W
D0
0
1
0