IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 222

• Manufacturer Part Number: IDT82V2108PX8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX8

IDT82V2108
T1 / J1 Transmit Interface Configuration (004H, 084H, 104H, 184H, 204H, 284H, 304H, 384H)
FIFOBYP:
mode.
TAISEN:
MTLD.
TSCCKBFALL:
MTSCFS. This bit is valid in Transmit Clock Slave mode and Transmit Multiplexed mode.
TSFSRISE:
Master mode, the signal on the TSFSn pin is updated on the falling edge of LTCKn.
ter mode, the signal on the TSFSn pin is updated on the rising edge of LTCKn.
TSDFALL:
LTCKRISE:
Programming Information
Bit Name
Default
Bit No.
= 0: The falling edge is selected.
= 1: The rising edge is selected.
In Receive Multiplexed mode, the RSCCKRISE of the eight framers must be set to the same value.
Type
This bit decides whether the transmit data should pass through or bypass the Transmit Jitter Attenuation FIFO. The bit is valid in Clock Slave
= 0: The data to be transmitted passes through the TJAT FIFO.
= 1: The TJAT FIFO is bypassed. The delay is reduced by typically 24 bits.
This bit enables the line interface to generate an un-framed all-’One’s Alarm Indication Signal on the TLDn pin or the corresponding framer on
= 0: Normal operation.
= 1: TLDn or the corresponding framer on MTLD transmits all ‘One’s.
This bit selects the active edge of TSCCKB/MTSCCKB to sample the data on the corresponding TSDn/MTSD, TSSIGn/MTSSIG and TSCFS/
= 0: The rising edge is selected.
= 1: The falling edge is selected.
The TSCCKBFALL of the eight framers should be set to the same value.
This bit is valid in Transmit Clock Slave TSFS Enabled mode and Transmit Clock Master mode.
= 0: In Transmit Clock Slave TSFS Enabled mode, the signal on the TSFSn pin is updated on the falling edge of TSCCKB. In Transmit Clock
= 1: In Transmit Clock Slave TSFS Enabled mode, the signal on the TSFSn pin is updated on the rising edge of TSCCKB. In Transmit Clock Mas-
This bit selects the active edge of LTCKn to sample the data on the corresponding TSDn in Transmit Clock Master mode.
= 0: The TSDn is sampled on the rising edge of LTCKn.
= 1: The TSDn is sampled on the falling edge of LTCKn.
This bit selects the active edge of LTCKn to update the data on the corresponding LTDn.
= 0: The falling edge is selected.
= 1: The rising edge is selected.
FIFOBYP
R/W
7
0
TAISEN
R/W
0
6
5
Reserved
4
212
TSCCKBFALL
R/W
3
0
TSFSRISE
R/W
2
0
T1 / E1 / J1 OCTAL FRAMER
TSDFALL
R/W
1
0
March 5, 2009
LTCKRISE
R/W
0