IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 274

• Manufacturer Part Number: IDT82V2108PX8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX8

IDT82V2108
T1 / J1 RHDLC Receive Data Link 2 Control (TXCISEL = 0) (070H, 0F0H, 170H, 1F0H, 270H, 2F0H, 370H, 3F0H)
DL2_EVEN:
DL2_ODD:
DL2_TS[4:0]:
DL2_ODD are both logic 0.
T1 / J1 RHDLC Data Link 2 Bit Select (TXCISEL = 0) (071H, 0F1H, 171H, 1F1H, 271H, 2F1H, 371H, 3F1H)
DL2_BITn:
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
When the TXCISEL (b3, T1/J1-00DH) is ‘0’, this register is used for the Receive HDLC #2.
= 0: The data is not extracted from the even frames.
= 1: The data is extracted from the even frames.
= 0: The data is not extracted from the odd frames.
= 1: The data is extracted from the odd frames.
These bits binary define one channel of even and/or odd frames to extract the data from. They are invalid when the DL2_EVEN and the
When the TXCISEL (b3, T1/J1-00DH) is ‘0’, this register is used for the Receive HDLC #2.
= 0: The data is not extracted from the corresponding bit.
= 1: The data is extracted from the corresponding bit of the assigned channel.
These bits are invalid when the DL2_EVEN and the DL2_ODD are both logic 0.
The DL1_BIT[7] corresponds to the first bit (MSB) of the selected channel.
DL2_BIT[7]
DL2_EVEN
R/W
R/W
7
0
7
0
DL2_BIT[6]
DL2_ODD
R/W
R/W
6
0
6
0
DL2_BIT[5]
Reserved
R/W
5
5
0
DL2_BIT[4]
DL2_TS[4]
R/W
R/W
4
0
4
0
264
DL2_BIT[3]
DL2_TS[3]
R/W
R/W
3
0
3
0
DL2_TS[2]
DL2_BIT[2]
R/W
R/W
2
0
2
0
T1 / E1 / J1 OCTAL FRAMER
DL2_BIT[1]
DL2_TS[1]
R/W
R/W
1
0
1
0
March 5, 2009
DL2_TS[0]
DL2_BIT[0]
R/W
R/W
0
0
0
0